Substrateless Chip-Scale Package Design
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Solution Overview
Problem
Current microelectronic device packaging methods using carrier substrates increase the size and cost of integrated circuit packages, as they are not optimal for all applications.
Innovation Solution
The development of a substrateless package approach, where a die is encased with conductive pillars and an encapsulant material, such as molding material, to form a chip-scale package or module, allowing for direct coupling of solder bumps with the conductive pillars for electrical connection without the need for a carrier substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If carrier substrates are used to mount die, then the package provides structural support and electrical connections, but the overall size and expense of the package increases
Solution Approach 1:
The patent removes the carrier substrate from the traditional packaging structure, extracting the unnecessary component that increases package size. The die is directly encapsulated with molding compound, eliminating the substrate while maintaining structural integrity through the encapsulant material and conductive pillar design.
Solution Approach 2:
The patent merges the functions of the carrier substrate into the encapsulant material and conductive pillars. The encapsulant provides both structural support and protection, while the conductive pillars provide electrical connections, combining multiple functions into integrated components rather than separate substrate-based systems.
2Reliability
If carrier substrates are used to mount die, then the package provides structural support and electrical connections, but the overall expense of the package increases
Solution Approach 1:
The patent extracts and eliminates the carrier substrate, which is a costly component in traditional packaging. By removing this expensive element and replacing it with a more cost-effective encapsulation approach using molding compound and conductive pillars, the overall manufacturing cost is reduced while maintaining necessary structural support.
Solution Approach 2:
The patent employs cost-effective materials such as molding compound for encapsulation instead of expensive carrier substrates. The conductive pillars provide necessary electrical connections using simpler, more affordable structures, reducing overall package expense while maintaining functional reliability.
3Ease of manufacture
If solder bumps are directly coupled with conductive pillars, then electrical connections are achieved without carrier substrate, but the alignment precision must be maintained
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process, including forming conductive pillars with precise dimensions and positions before die attachment, and using alignment marks or features on the die to ensure proper positioning. The encapsulant material is applied in a controlled manner to maintain alignment between solder bumps and conductive pillars during the encapsulation process.
Solution Approach 2:
The patent controls critical parameters such as the diameter, height, and position of conductive pillars, as well as the viscosity and curing properties of the encapsulant material, to ensure proper alignment and electrical connection between solder bumps and conductive pillars without requiring a carrier substrate.
Data Source
AI summary
Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.