Subthreshold Semiconductor Circuit for Low-Power Product-Sum Computing
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Solution Overview
Problem
Transistor characteristics in silicon-based integrated circuits are susceptible to temperature changes, leading to performance issues and increased power consumption due to heat generation, and existing digital multiplier circuits require large areas and power consumption for neural network operations.
Innovation Solution
A semiconductor device incorporating transistors with metal oxide channels and a novel circuit design that performs product-sum operations using subthreshold region currents, reducing power consumption and circuit area while minimizing heat effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon-based transistors are used in integrated circuits, then high processing speed can be achieved, but transistor characteristics change due to temperature increase, leading to performance degradation
Solution Approach 1:
The patent changes the material parameter of the transistor channel from silicon to metal oxide, which fundamentally alters the temperature dependence characteristics. Metal oxide transistors exhibit superior thermal stability compared to silicon-based transistors, allowing the circuit to maintain reliable operation at elevated temperatures without characteristic drift
Solution Approach 2:
The patent employs a hybrid approach by combining metal oxide transistors for temperature-sensitive operations with silicon-based transistors for high-speed operations. This composite material strategy allows the system to leverage the thermal stability of metal oxides while maintaining the high processing speed capabilities of silicon, thereby resolving the contradiction between speed and reliability
2Productivity
If digital multiplier circuit and digital adder circuit are used for product-sum operation, then arithmetic operation can be performed, but circuit area and power consumption increase
Solution Approach 1:
The patent replaces the conventional digital logic-based multiplier and adder circuits with an analog circuit that directly performs product-sum operations. By using analog voltage or current signals and operational amplifiers, the circuit achieves multiplication and addition in a single operation without requiring separate digital stages, thereby significantly reducing circuit area
Solution Approach 2:
The patent merges the multiplication function and addition function into a single integrated analog circuit block. Instead of having separate multiplier circuits and adder circuits that would require multiple logic gates and interconnections, the analog implementation combines both operations in one unified structure, reducing overall circuit complexity and area
3Productivity
If digital multiplier circuit and digital adder circuit are used for product-sum operation, then arithmetic operation can be performed, but power consumption increases
Solution Approach 1:
The patent substitutes the high-power digital logic circuits with low-power analog circuits. Analog operations using operational amplifiers and passive components consume significantly less power than digital multiplier and adder circuits, which require multiple switching transistors and generate dynamic power consumption. This substitution enables arithmetic operations with reduced power overhead
Solution Approach 2:
The patent implements clock-gating techniques where the analog computation circuits are activated only during the specific time periods when product-sum operations are required. By using periodic enable signals and clock control, the circuit remains in a low-power standby state during idle periods, thereby reducing average power consumption while maintaining full arithmetic operation capability when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves low power consumption, reduced circuit area, and maintains performance by utilizing metal oxide transistors in subthreshold regions for product-sum operations, inhibiting performance degradation from heat.
Implementation Method 1
Each memory element of the product-sum operation circuit outputs current corresponding to a product of data corresponding to a multiplier stored in each memory element and input data corresponding to a multiplicand by using operation in a subthreshold region of a transistor containing silicon in its channel formation region
Implementation Method 2
The transistor characteristics, field-effect mobility, and the like of a transistor containing silicon in its channel formation region easily change due to a temperature change. In particular, in the case where a product-sum operation circuit or the like is formed as an integrated circuit, heat generated at the time of driving increases the temperature of the integrated circuit, which changes the characteristics of the transistors included in the integrated circuit
Data Source
AI summary
A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.