Sub-threshold Flash Memory Voltage Reference Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current non-volatile semiconductor memory systems face high power consumption in sleep or stand-by modes due to the need to keep circuits alive for fast memory access, and turning them off results in unacceptably long startup times for memory operations.
Innovation Solution
The implementation of a non-volatile memory system with a voltage reference and bias generating facility that includes sub-threshold reference circuits, allowing for quick switching between sleep and active modes, reducing power usage and startup times by maintaining the sub-threshold reference circuit active while the bias circuit is in a stand-by state, and enabling rapid transition to active mode within less than 10 read cycle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If circuits are kept alive for fast memory access, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management by enabling the memory system to switch between different operational states (active, sleep, stand-by) with different power consumption levels. The voltage reference circuit is selectively enabled based on operational mode, allowing the system to optimize between speed and power consumption dynamically.
Solution Approach 2:
The patent changes the operational parameters of the voltage reference circuit by implementing sub-threshold operation mode. This allows the circuit to operate at very low current levels (sub-threshold current) while maintaining functional operation, thereby reducing power consumption during sleep and stand-by modes while still enabling relatively fast wake-up.
2Use of energy by moving object
If circuits are turned off to reduce power consumption, then power consumption decreases, but startup time increases
Solution Approach 1:
The patent implements preliminary action by maintaining the voltage reference circuit in a partially active state during sleep mode. The sub-threshold reference circuit remains operational at minimal current, preparing the system for rapid activation. This preliminary maintenance of circuit readiness eliminates the need for full initialization during wake-up, achieving fast startup times.
Solution Approach 2:
The patent implements periodic action through selective enabling of the voltage reference circuit based on operational mode. The circuit transitions between active, sleep, and stand-by states periodically based on system requirements, optimizing the balance between power consumption and startup performance.
3Loss of time
If sub-threshold reference circuit is maintained active, then wake-up time is reduced, but stand-by current increases
Solution Approach 1:
The patent applies parameter changes by operating the voltage reference circuit in sub-threshold mode during stand-by state. This operational mode allows the circuit to maintain functionality with extremely low current consumption (sub-threshold current levels) while still being capable of rapid activation. The circuit parameters are optimized to achieve both low stand-by current and fast wake-up performance.
Data Source
AI summary
A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.