Sub-Threshold FPGA Delay Compensation for Low-Power Operation
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) typically require higher power consumption and are slower than application-specific integrated circuits (ASICs), and existing reconfigurable circuit designs are sensitive to semiconductor processing, operating voltage, and temperature (PVT) variations, limiting their viability in low-power applications.
Innovation Solution
The design employs sub-threshold currents and dynamic body biasing to reduce power consumption and compensate for PVT variations, using a semiconductor device with logic blocks and programmable interconnects, including a delay detector and charge pump to adjust delays, allowing FPGAs to operate at extremely low power levels while maintaining performance across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If FPGAs operate at normal voltage levels, then they provide sufficient speed and performance, but power consumption increases significantly
Solution Approach 1:
The patent changes the operating voltage parameter from normal levels to sub-threshold levels (below the transistor threshold voltage), enabling ultra-low power operation. This parameter change fundamentally alters the operating regime of the FPGA, allowing it to function at 100-500 times lower power consumption while using delay compensation to maintain timing accuracy.
2Use of energy by moving object
If FPGAs are operated at sub-threshold voltages to reduce power, then power consumption decreases dramatically, but delay variations due to PVT variations increase
Solution Approach 1:
The patent implements a feedback mechanism using delay detectors that continuously measure actual signal delays in logic blocks and interconnects. These measured delays are fed back to control circuits that adjust timing parameters dynamically, compensating for PVT variations and maintaining reliable operation despite operating at sub-threshold voltages.
Solution Approach 2:
The patent introduces dynamic adjustment capabilities where timing parameters are not fixed but continuously adapted based on real-time delay measurements. This dynamic approach allows the FPGA to maintain performance consistency across varying process, voltage, and temperature conditions by actively adjusting to changing parameters rather than being static.
3Reliability
If delay compensation circuits are added to sub-threshold FPGAs, then performance consistency improves, but device complexity increases
Solution Approach 1:
The patent divides the FPGA into segments (logic blocks and interconnect segments), each with its own delay detector and compensation mechanism. This segmentation allows delay compensation to be applied locally to specific regions rather than requiring a monolithic complex control system, reducing overall device complexity while maintaining performance consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves power reductions of 100 to 500 times lower than traditional methods, enabling battery-free, ambient light-powered reconfigurable circuits with reduced non-recurring engineering costs and improved applicability, while maintaining performance consistency across PVT variations.
Implementation Method 1
The reference output signal is generated by a sub-threshold leakage current
Implementation Method 2
A phase detector is adapted to determine a delay by comparing the reference output phase signal to a reference delay signal
Implementation Method 3
A charge pump responsive to an indication of the delay biases the reference output signal toward the reference delay signal
Implementation Method 4
A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value
Data Source
AI summary
According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.