Low-Voltage Level Shifter Using Reversible Current Mirror
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Solution Overview
Problem
Voltage level shifters face challenges in operating speed and semiconductor surface area usage when dealing with low supply voltages, particularly in microcontroller applications where subthreshold logic is employed, leading to inefficiencies and increased power consumption.
Innovation Solution
A low voltage level shifter design utilizing a reversible current mirror circuit with equally sized NMOS and PMOS transistors, which operates in forward and reverse modes to efficiently switch between low and high supply voltages, reducing transition delay and power consumption while occupying less semiconductor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional voltage level shifters are used with low supply voltages, then power consumption is reduced, but operation speed decreases and transition delay increases
Solution Approach 1:
The circuit uses dynamic switching of transistor pairs (first and second transistor pairs for low voltage, third and fourth transistor pairs for high voltage) to adapt to different voltage domains. The reversible current mirror dynamically adjusts current flow direction based on voltage level, enabling fast transitions while maintaining low power consumption in subthreshold operation.
Solution Approach 2:
The invention changes the operating parameters of the current mirror by using equally sized NMOS and PMOS transistors with optimized width-to-length ratios. This parameter optimization allows the circuit to operate efficiently at low supply voltages (0.4V-0.8V) while maintaining fast switching speeds and low power consumption.
2Speed
If larger voltage level shifters are used to accommodate lower supply voltages, then operation speed is maintained, but semiconductor surface area increases
Solution Approach 1:
The circuit employs asymmetric transistor sizing within symmetric functional blocks. The NMOS and PMOS transistors in each pair have different width-to-length ratios optimized for their specific roles, allowing compact layout while maintaining fast switching performance at low voltages without requiring larger overall circuit area.
Solution Approach 2:
The voltage level shifter uses a nested structure where the reversible current mirror is embedded within the transistor pair configuration. The third and fourth transistor pairs are nested within the same current mirror structure as the first and second pairs, reducing overall area while maintaining functionality across voltage domains.
3Device complexity
If conventional current mirror designs are used, then circuit simplicity is maintained, but transition delay increases at low voltages
Solution Approach 1:
The reversible current mirror is pre-configured with equally sized NMOS and PMOS transistors and optimized aspect ratios before operation. This preliminary design ensures that when voltage transitions occur, the current mirror can immediately respond with minimal delay, as all transistors are pre-positioned for optimal performance at the target voltage level.
Solution Approach 2:
The current mirror acts as an intermediary between the low-voltage input domain and high-voltage output domain. By using equally sized NMOS and PMOS transistors as the intermediary elements, the circuit achieves fast current transfer and voltage level conversion with minimal transition delay while maintaining circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables faster operation and reduced power consumption compared to traditional designs, maintaining effectiveness even at lower supply voltages, thus addressing the limitations of existing voltage level shifters in microcontroller interfaces.
Implementation Method 1
A pair of equally sized N-channel, semiconductor metal oxide field-effect (NMOS) transistors N11-N14 and a pair of equally sized P-channel, metal oxide semiconductor field-effect (PMOS) transistors P11-P14
Data Source
AI summary
A low voltage level shifter that is suitable for use with subthreshold logic. In one embodiment, the low voltage level shifter includes first and second input transistors coupled to first and second input nodes, respectively, that receive complementary low voltage input signals. A circuit is coupled to the first and second input transistors and to first and second output nodes that generate complementary high voltage output signals. The circuit is configured to transmit a first current to the second output node when the first input transistor is activated, wherein the first current is substantially equal to current drawn by the first input transistor when it is activated. The circuit is also configured to transmit a second current to the first output node when the second input transistor is activated, wherein the second current is substantially equal to current drawn by the second input transistor when it is activated.