Sub-threshold Memory Cell Circuit for High Density and Robustness
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Solution Overview
Problem
Sub-threshold memory cell designs face challenges in achieving high density and robustness while maintaining low power consumption, with issues such as degraded static noise margin, weakened writing performance, and susceptibility to process deviations, which are not adequately addressed by existing designs that compromise on memory cell density.
Innovation Solution
A high-density and high-robustness sub-threshold memory cell circuit is designed with seven transistors, featuring double-end writing and single-end reading capabilities, utilizing two PMOS and five NMOS transistors with specific connections to form phase inverters and a cut-off transistor, allowing for dynamic switching and minimizing transistor size, thus balancing read, write, and hold noise margins without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If sub-threshold design is used to reduce power consumption, then power consumption is reduced significantly, but static noise margin is degraded severely
Solution Approach 1:
The memory cell is divided into two separate read ports, allowing independent read operations to occur simultaneously. This segmentation enables the read operation to be performed without interfering with the write operation, thereby maintaining adequate noise margins while operating in sub-threshold voltage regime for low power consumption
Solution Approach 2:
A dedicated write-assist circuit is introduced as an intermediary component to enhance the write operation. This circuit provides additional drive strength to overcome the weakened writing performance inherent in sub-threshold design, ensuring reliable data writing while maintaining low power operation
2Use of energy by moving object
If sub-threshold design is used to reduce power consumption, then power consumption is reduced significantly, but writing performance is weakened
Solution Approach 1:
A dedicated write-assist circuit is introduced as an intermediary component to enhance the write operation. This circuit provides additional drive strength to overcome the weakened writing performance inherent in sub-threshold design, ensuring reliable data writing while maintaining low power operation
3Reliability
If transistor size is increased to improve tolerance to process deviations, then tolerance to process deviations is improved, but density is degraded
Solution Approach 1:
The memory cell design incorporates dynamic sizing techniques where transistor widths are optimized for sub-threshold operation. The design uses minimum transistor sizes compatible with sub-threshold voltage operation, achieving both high density and adequate process tolerance through dynamic optimization rather than static large-sizing
Solution Approach 2:
The design changes the operating voltage parameter to sub-threshold levels (200-300mV), which fundamentally alters the transistor characteristics. This parameter change enables the use of minimum-sized transistors while maintaining reliability, as sub-threshold operation provides inherent noise immunity and process tolerance without requiring large device sizes
4Reliability
If two NMOS transistors are added to improve read noise margin, then read noise margin is improved, but chip area increases by 30%
Solution Approach 1:
The memory cell is divided into two separate read ports, allowing independent read operations to occur simultaneously. This segmentation enables the read operation to be performed without interfering with the write operation, thereby maintaining adequate noise margins while operating in sub-threshold voltage regime for low power consumption
Solution Approach 2:
The memory cell structure is designed to perform multiple functions using the same transistors. The cross-coupled inverter structure serves both as storage elements and as read path amplifiers, eliminating the need for additional dedicated read transistors and reducing overall cell area
Data Source
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AI summary
A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors P1 and P2 and five NMOS transistors N1∼N5, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N3, N4, and N5 is connected with the local grid electrode respectively; the base electrode of the NMOS transistors N1 and N2, are grounded respectively; the NMOS transistor N1 form an phase inverter with the PMOS transistor P1, and the NMOS transistor N2 form another phase inverter with the PMOS transistor P2; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N5, the output end of the phase inverter N1 and P1 directly connected to the input end of the phase inverter N2 and P2, and the output end of the phase inverter N2 and P2 connected to the input end of the phase inverter N1 and P1 via the cut-off NMOS transistor N5; the NMOS transistor N3 is connected with the write bit line (WBL) of the phase inverter N1 and P1, and the NMOS transistor N4 is connected with the NOT WBL and read word line (RWL) of the phase inverter N2 and P2.