Deep Neural Network Accelerator With Sub-Threshold Memory Compute
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Solution Overview
Problem
The high computational demands of deep neural networks are not efficiently addressed by CPUs, and GPUs have low utilization rates due to their structural limitations, leading to inefficiencies in training times and resource consumption.
Innovation Solution
A deep neural network accelerator with a memory cell array structure, comprising memory cells with transistors having a charge storage layer, and a method for matrix computation using a row driver and column driver to measure voltage drops in memory cells, optimizing threshold voltages for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU is used for deep neural network training, then computation can be performed, but training time is excessively long
Solution Approach 1:
The patent replaces traditional CPU/GPU computational architectures with a memory-based computational system using charge-coupled device (CCD) circuits. The CCD-based memory cell array performs matrix multiplication computations directly in memory, substituting the von Neumann architecture's separate processing and memory units with an integrated system where computation occurs during memory operations, dramatically reducing training time
Solution Approach 2:
The patent creates a universal computational platform where the CCD-based memory cell array can perform various deep neural network operations including matrix multiplication, convolution, and other computational tasks. The same hardware structure handles multiple types of AI computations, making the system versatile and highly efficient for different deep learning workloads
2Productivity
If GPU is used for deep neural network computation, then parallel processing capability is improved, but utilization rate decreases due to structural limitations
Solution Approach 1:
The patent extracts the computational function from traditional GPU architecture and relocates it to the memory cell array itself. By removing the need for separate processing units and utilizing the memory structure for computation, the system achieves parallel processing without the structural overhead of conventional GPUs, improving utilization rate while maintaining parallel capability
Solution Approach 2:
The patent enables the memory cell array to perform computations autonomously during normal memory operations. The CCD-based memory cells inherently perform analog computations through their electrical characteristics, eliminating the need for additional control logic or processing units, thus reducing structural complexity while maintaining high parallel processing efficiency
3Quantity of substance
If traditional memory architecture is used, then data storage is achieved, but computational efficiency for deep neural networks is low
Solution Approach 1:
The patent merges the data storage function and computational function into a single integrated system. The CCD-based memory cell array simultaneously stores weight data and performs matrix multiplication computations, eliminating the data movement bottleneck between separate memory and processing units, thereby achieving both high storage capacity and high computational efficiency
Solution Approach 2:
The patent replaces the traditional separation of storage and computation with a unified memory-based computational approach. By using the electrical properties of CCD memory cells to perform analog computations directly on stored data, the system achieves computational efficiency without sacrificing storage capacity, as both functions coexist in the same physical structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides an area and cost-effective deep neural network accelerator capable of performing matrix computations with low latency and high precision, leveraging a sub-threshold region for efficient AI computations without the need for accumulators.
Implementation Method 1
memory cells, each composed of a transistor having a charge storage layer
Implementation Method 2
a gate-source voltage of the first transistor is a voltage of a sub-threshold region
Data Source
AI summary
Disclosed are a deep neural network accelerator and an electronic device including the same. The deep neural network accelerator may include a memory cell array including memory cells arranged along word lines and bit lines, wherein at least one of the memory cells includes a first transistor programmed such that a threshold voltage thereof is shifted by a shift voltage corresponding to a weight value; a row driver configured to apply a word line voltage corresponding to an input activation value to the word lines corresponding to the first transistor; and a column driver configured to measure a voltage drop caused by memory cells corresponding to a first bit line among the bit lines, wherein a gate-source voltage of the first transistor may be a voltage of a sub-threshold region.