Subthreshold MOS Circuit for Large Resistance in Small IC Area
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Solution Overview
Problem
Existing integrated circuits face challenges in generating large electrical resistance values without significant area consumption, as traditional resistor types like poly-silicon resistors occupy substantial space, and cascading transistors to achieve high resistance also takes up considerable IC real estate.
Innovation Solution
Employing metal-oxide semiconductor (MOS) devices biased in the sub-threshold region to generate large electrical resistance, where transistors are configured to operate in the sub-threshold region with voltage-limiting devices and bias circuits, allowing for controlled resistance values with reduced area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional resistor types like poly-silicon resistors are used to generate large resistance values, then the desired resistance is achieved, but the area consumption on the integrated circuit increases significantly
Solution Approach 1:
The patent changes the operating parameters of the MOS transistor by biasing it in the sub-threshold region where the gate-to-source voltage is less than the threshold voltage. This parameter change enables the transistor to exhibit high resistance characteristics (greater than 1 MΩ) without requiring large physical area, thus resolving the contradiction between achieving large resistance values and minimizing area consumption
Solution Approach 2:
The patent substitutes traditional passive resistor structures (poly-silicon resistors) with an active transistor-based resistance generation mechanism. By using a MOS transistor operated in sub-threshold mode, the invention replaces the conventional resistor implementation with a more area-efficient alternative that achieves the same electrical resistance function
2Reliability
If cascading transistors is used to achieve high resistance values, then the desired resistance is obtained, but the area consumption on the integrated circuit increases considerably
Solution Approach 1:
Instead of cascading multiple transistors to achieve high resistance, the patent changes the operating parameter of a single MOS transistor to the sub-threshold region. This single-transistor approach with modified biasing conditions achieves the same high resistance effect that would otherwise require multiple cascaded transistors, thereby reducing area consumption
3Area of stationary object
If metal-oxide semiconductor devices are biased in the sub-threshold region, then area consumption is reduced, but the gate-to-source voltage control becomes more complex
Solution Approach 1:
The patent introduces a voltage-limiting device as an intermediary component connected between the gate and source of the MOS transistor. This device automatically limits the gate-to-source voltage to remain below the threshold voltage, maintaining sub-threshold operation without requiring complex external control circuitry. The voltage-limiting device simplifies the overall control mechanism while enabling area-efficient resistance generation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the generation of large resistance values with reduced area consumption, potentially using lower capacitance in RC filters, offering a more efficient use of integrated circuit space and improved noise filtering capabilities.
Implementation Method 1
the first transistor operates in a sub-threshold region
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor 210, 220 having a gate, a source connected with a first node 214 of the circuit, and a drain connected with a second node 216 of the circuit. The circuit may also include a voltage-limiting device 224, 226 connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor 212, 222 configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.