Sub-Threshold Reference Voltage Circuit for Low-Jitter CML
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current System-On-Chip (SOC) clock distribution networks face challenges in maintaining low jitter and stability due to voltage fluctuations, limiting the placement of Current Mode Logic (CML) circuits and degrading jitter performance, especially when connected to unregulated power supplies.
Innovation Solution
A reference voltage generation circuit using transistors in sub-threshold mode operation, coupled with an operational amplifier for feedback control, maintains a stable reference voltage independent of supply voltage variations, ensuring consistent current mode logic signaling across the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CML circuits are connected to unregulated power supplies to enable broader placement across the chip, then floorplanning flexibility is improved, but jitter performance degrades due to voltage fluctuations
Solution Approach 1:
The patent introduces an on-chip reference voltage generation circuit as an intermediary component between the unregulated power supply and the CML circuits. This circuit generates a stable reference voltage that is independent of supply voltage variations, allowing CML circuits to be placed anywhere on the chip while maintaining low jitter performance. The reference voltage circuit acts as a mediator that isolates the CML circuits from power supply fluctuations.
Solution Approach 2:
The patent implements local reference voltage generation at each CML buffer location rather than relying on a global regulated power supply. Each CML buffer has its own reference voltage generation circuit that creates a locally stable voltage reference, enabling independent operation and placement flexibility across different regions of the chip with varying power supply conditions.
2Reliability
If a regulated power supply is used to maintain stable voltage for CML circuits, then jitter performance is improved, but distribution complexity increases across the chip
Solution Approach 1:
The patent divides the power distribution system into multiple independent reference voltage generation circuits distributed across the chip, each serving local CML circuits. This segmentation eliminates the need for a single complex global regulated power supply network, reducing distribution complexity while maintaining stable voltage references at each location.
Solution Approach 2:
Each CML buffer location generates its own reference voltage using the on-chip reference voltage generation circuit, making the system self-sufficient at each node. This eliminates the need for complex centralized power regulation and distribution infrastructure, as each local circuit serves itself with a stable voltage reference independent of the main power supply network.
3Device complexity
If simple resistor-divider reference voltage is used to reduce circuit complexity, then device complexity is reduced, but jitter increases above optimal levels
Solution Approach 1:
The patent changes the operating parameters of the transistors by biasing them in the sub-threshold region, where they exhibit exponential current-voltage characteristics. This parameter change enables the creation of a reference voltage circuit with relatively simple structure that achieves superior voltage stability and low jitter performance, outperforming traditional resistor-divider approaches while maintaining acceptable complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces jitter and delay variations while optimizing power consumption, allowing for a more efficient and stable clock distribution network even under varying supply voltages, improving overall SOC performance.
Implementation Method 1
The second and third transistors are sized such that they remain in sub-threshold mode operation during operation with an expected range of the supply voltage
Implementation Method 2
coupled with an operational amplifier for feedback control, maintains a stable reference voltage independent of supply voltage variations
Data Source
AI summary
A reference voltage generation circuit for use with current mode logic includes a first transistor of a first conductivity type configured to operate as a diode-connected resistor with a source terminal coupled to a first voltage supply terminal for conducting a supply voltage and a gate terminal coupled to a drain terminal. Second and third transistors of a second conductivity type are coupled in series between the drain terminal of the first transistor and a second voltage supply terminal. Gate terminals of the second and third transistors coupled to the gate terminal of the first transistor. A reference voltage is obtained between the second and third transistors. The first and second NMOS transistors are sized such that they remain in sub-threshold mode operation during operation with an expected range of the supply voltage. Current mode logic circuits are also provided using the reference voltage generation circuit.