Subtractive Memory Compiler Template Design
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Solution Overview
Problem
Conventional memory compiler methods, particularly for complex memories like DRAM or flash, rely on time-consuming and error-prone manual processes due to their additive nature, which is inefficient and costly, and not easily scalable for generating various configurations.
Innovation Solution
A subtractive approach to memory compiler design, starting with a template of maximum capacity and gradually removing components to generate smaller memory configurations, utilizing One-Time Programmable (OTP) memory cells with polysilicon electrical fuse or anti-fuse elements and diodes as program selectors, allowing for easier reduction of memory array size and component subtraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual processes are used to build memory compilers for complex memories like DRAM or flash, then design flexibility and customization are improved, but time consumption and error rates increase significantly
Solution Approach 1:
The patent creates a master template containing all necessary memory components (bit cells, decoders, sense amplifiers, address buffers, control logic) that can be copied and instantiated multiple times. This template-based approach allows automated generation of different memory configurations by simply modifying instantiation parameters rather than manually redesigning each configuration, thereby reducing time consumption while maintaining design flexibility.
Solution Approach 2:
The patent enables generation of different memory configurations by changing parameters such as memory capacity, I/O counts, aspect ratios, and technology node without requiring manual redesign. The compiler accepts these parameters as inputs and automatically adjusts the template instantiation accordingly, resolving the contradiction between adaptability and time consumption.
2Adaptability or versatility
If manual processes are used to build memory compilers for complex memories, then complex configurations can be achieved, but human error and costs increase
Solution Approach 1:
By using a verified master template that is copied rather than manually recreated, the patent eliminates human error associated with manual design processes. The template has been pre-verified for correctness, and copying it ensures consistent, error-free generation across all configurations, thereby improving reliability while maintaining the ability to handle complex configurations.
Solution Approach 2:
The memory compiler performs self-verification and automatic configuration generation without human intervention. The system automatically checks for design rule compliance, validates configurations, and generates appropriate code, reducing human error while handling complex memory configurations that would be prone to manual mistakes.
3Adaptability or versatility
If additive approach (tiling) is used to build memory compilers, then various memory configurations can be generated, but the process becomes time-consuming and not easily scalable
Solution Approach 1:
Instead of the conventional additive approach where small units are tiled together to build larger structures, the patent uses a subtractive approach where a complete master template is created and then selectively instantiated in different quantities and configurations. This inversion of the building methodology dramatically improves productivity while maintaining the ability to generate various memory configurations through parameter adjustment rather than incremental assembly.
Solution Approach 2:
The patent performs preliminary action by creating a complete, verified master template that contains all necessary components before actual memory generation begins. This pre-prepared template can then be rapidly instantiated multiple times with different parameters, eliminating the time-consuming incremental assembly process while maintaining configuration flexibility.
4Ease of manufacture
If conventional tiling methods are used for memory compiler generation, then basic memory structures can be built, but scaling to various configurations becomes inefficient and costly
Solution Approach 1:
The patent creates a universal master template that serves multiple functions: it can generate different memory capacities, I/O configurations, aspect ratios, and support different technology nodes. This single template replaces multiple specialized designs, making the generation process simpler while dramatically improving scaling efficiency across various memory configurations.
Solution Approach 2:
The patent enables easy scaling to various configurations by allowing parameter changes in the template instantiation process. Instead of creating new designs for each configuration, the system modifies parameters such as array dimensions, decoder sizes, and I/O counts, thereby maintaining generation simplicity while achieving efficient scaling across diverse memory requirements.
Data Source
AI summary
A memory compiler to generate a set of memories is based on a subtraction approach from a set of templates (memory templates), including at least one layout database and auxiliary design databases, by software. The software can be based on general-purpose programming language or a layout-specific language. The compiled memories can be generated by reducing the memory array sizes in row and/or column directions by moving, deleting, adding, sizing, or stretching the layout objects, and disabling the high order addresses, etc. from the memory template by software. The new auxiliary design databases, such as layout phantom, behavior model, synthesis view, placement-and-routing view or datasheet, can also be generated by modifying some parameters from the memory template by software. One-time programmable memory using junction diode, polysilicon diode, or isolated active-region diode as program selector in a cell can be generated accordingly.