Subtractive Metal Interconnects With Low-Resistivity Liner Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional subtractive metal interconnects, such as those using tungsten, face challenges with high resistivity and electromigration issues in narrow lines due to grain boundary scattering, making them impractical for feature sizes below 50 nm.
Innovation Solution
The use of Ti, Ta, TaN, or combinations thereof as liner layers, followed by physical vapor deposition of metal layers with a sputter operation to achieve low resistivity, and selective deposition of etch stop layers to minimize residual materials and prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional subtractive metal interconnects (e.g., tungsten) are used, then electromigration resistance is improved, but resistivity increases due to grain boundary scattering in narrow lines
Solution Approach 1:
The patent changes the material composition parameters by introducing specific liner layer materials (Ti, Ta, TaN) and their thickness ratios. By adjusting the liner layer composition and thickness (e.g., Ti layer thickness between 1-10 nm), the patent optimizes the balance between electromigration resistance and resistivity, achieving low resistivity interconnects with improved reliability
Solution Approach 2:
The patent employs composite material structures consisting of multiple layers: liner layers (Ti, Ta, TaN), barrier layers, and copper fill materials. This composite approach combines the advantages of different materials - the liner layers provide electromigration resistance while enabling low resistivity copper interconnects, thus resolving the contradiction between reliability and harmful resistivity effects
2Area of moving object
If feature sizes are reduced below 50 nm, then device integration density is improved, but copper damascene processes become impractical due to increased grain boundary scattering and electromigration risk
Solution Approach 1:
The patent applies preliminary action by depositing specially engineered liner layers (Ti, Ta, TaN) on the substrate before copper deposition. These liner layers are prepared in advance with specific thicknesses and compositions to prevent copper diffusion and reduce electromigration effects, enabling reliable sub-50 nm interconnects that would otherwise be impractical with conventional copper damascene processes
3Ease of manufacture
If W and other metals are deposited on TiN, then subtractive metal interconnects are formed, but resistivity increases to 40 μΩ·cm or more
Solution Approach 1:
The patent changes the material parameters by replacing TiN with alternative liner layer materials (Ti, Ta, TaN) and optimizing their thickness. This parameter change reduces the resistivity from 40 μΩ·cm or more to significantly lower values, while maintaining the ease of manufacture for subtractive metal interconnects through standard PVD deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in metal interconnects with resistivity of 30 μΩ·cm or less, improved adhesion, and reduced electromigration, enabling reliable performance in small feature sizes.
Implementation Method 1
performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer
Implementation Method 2
depositing, by physical vapor deposition, a metal layer on the liner layer
Data Source
AI summary
Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.