Self-Aligned Via Formation Using Subtractive Etching
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Solution Overview
Problem
The existing dual-damascene fabrication techniques are impractical for forming interconnect structures at 10 nm Node and smaller feature sizes due to gap fill and resistivity constraints, necessitating a method that aligns vias without relying on the damascene scheme.
Innovation Solution
A subtractive process is employed to form self-aligned interconnect structures by etching a patterned stack of layers, including conductive and etch stop layers, to create pillars that extend from an underlying base layer, eliminating the need for filling micro conduits with conductive material and allowing for alignment relative to underlying metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual-damascene fabrication techniques are used, then vias can be self-aligned with metal lines, but gap fill and resistivity constraints make it impractical for 10 nm Node and smaller feature sizes
Solution Approach 1:
The patent inverts the traditional damascene approach by using a subtractive process instead of an additive one. Instead of filling trenches with conductive material, the method removes material to form vias through etching, thereby avoiding gap fill issues and resistivity constraints while maintaining via alignment precision
Solution Approach 2:
The patent changes the fundamental process parameter from additive (filling) to subtractive (etching). This parameter change enables via formation at 10 nm Node and smaller feature sizes by eliminating the physical constraints of material filling in narrow trenches, while the self-aligned etch process maintains alignment precision
2Ease of manufacture
If a subtractive process is used to form vias, then gap fill and resistivity constraints are eliminated, but a new method for aligning vias to metal lines must be developed
Solution Approach 1:
The patent employs self-aligned etching where the via alignment to metal lines is achieved automatically through the etch process itself, using the metal lines or underlying structures as alignment references. This self-service mechanism eliminates the need for separate alignment steps while maintaining precision
Solution Approach 2:
The patent performs preliminary patterning and etch stop layer formation before via etching, establishing alignment references and etch boundaries in advance. This preliminary action simplifies the subsequent via formation step while ensuring precise alignment to metal lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of self-aligned interconnect structures without voids, facilitating the progression to devices at the 10 nm Node and below, with high etch rate metal etches and passivation processes ensuring accurate and efficient interconnect formation.
Implementation Method 1
etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer
Data Source
AI summary
A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.