Sub-Vector Compression Layout for Lower Processor Wire Congestion
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Solution Overview
Problem
Current AI processor data compression methods using multiplexers result in severe wire congestion and increased area due to high vector processing parallelism, leading to manufacturing difficulties and costs.
Innovation Solution
A method and apparatus for compressing and decompressing vector data using a processor with a source vector register, multiple multiplexers, a data merging apparatus, and a data splitting apparatus, which divides and merges sub-vectors to reduce the number of multiplexers and wires required, implementing divide-and-conquer processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct compression of vector data using a set of multiplexers is implemented, then compression functionality is achieved, but wire congestion and processor area increase
Solution Approach 1:
The patent divides the vector data into multiple sub-vectors and processes them separately through different multiplexer sets. Instead of using one large multiplexer system to handle all 16 elements simultaneously, the data is segmented into groups (e.g., 4 elements per group with 4 multiplexer sets), reducing the complexity and wire congestion of each individual multiplexer while maintaining overall compression functionality.
2Speed
If high vector processing parallelism is implemented, then processing speed is improved, but wire congestion and manufacturing complexity increase
Solution Approach 1:
The patent segments the parallel processing into multiple stages where different multiplexer sets operate on different sub-vectors. This segmentation allows parallelism to be maintained across multiple independent pathways rather than requiring a single complex high-speed pathway, thereby reducing wire congestion while preserving processing speed.
Solution Approach 2:
The patent introduces a new dimension of organization by arranging multiplexer sets in a two-dimensional structure (multiple sets operating in parallel on different data segments) rather than a single linear pathway. This dimensional change allows the system to achieve high throughput through coordinated parallel operation of simpler units rather than requiring a single complex high-speed pathway.
3Productivity
If more multiplexers are arranged in sequence, then compression capability is improved, but manufacturing cost and difficulty increase
Solution Approach 1:
The patent segments the compression function across multiple identical or similar multiplexer sets rather than using one large complex multiplexer. This segmentation creates modular units that are easier to manufacture and test individually, reducing overall manufacturing difficulty and cost while maintaining compression capability.
Solution Approach 2:
The patent merges the output of multiple simpler multiplexer sets to achieve the overall compression function. Instead of manufacturing one complex multiplexer, multiple simpler multiplexers are combined through the data merging apparatus, reducing individual component complexity and manufacturing difficulty while achieving the same functional result.
Data Source
AI summary
The present subject matter relates to the field of data processing technologies. Source vector data is stored in a source vector register. The source vector data is divided into n source sub-vectors. The n source sub-vectors are in a one-to-one correspondence with n sets of multiplexers. First valid elements in a source sub-vector are selectively arranged by multiplexers in the n sets of multiplexers in the source vector data to obtain a target sub-vector. A data merging apparatus shifts and merges n target sub-vectors corresponding to the n source sub-vectors to obtain target vector data. A target vector register stores second valid elements in the target vector data. Through the method, the apparatus, and the device, a congestion level of wires can be effectively reduced, thereby significantly reducing an area of a processor.