Sub-word Finite State Machine Parallel Search Engine
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Solution Overview
Problem
Existing finite state machines (FSMs) face challenges in efficiently searching large data strings for patterns, particularly when dealing with variable patterns, due to high memory requirements and processing time, which becomes prohibitive for real-time applications like digital oscilloscopes generating high data rates.
Innovation Solution
The use of a parallel search engine comprising multiple sub-word FSMs, each processing a segment of the input data, with a combiner to verify matches across all sub-word FSMs, effectively emulating a single FSM to search for variable patterns, reducing memory needs and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single FSM is used to search for patterns in a data string, then the search can be performed sequentially, but the search time becomes prohibitive for long data strings and real-time processing applications
Solution Approach 1:
The patent divides a single FSM into multiple sub-word FSMs that process different segments of the input data in parallel. Each sub-word FSM handles a portion of the N-bit input word, allowing simultaneous processing of multiple data segments and significantly reducing search time for long data strings while maintaining real-time processing capability
Solution Approach 2:
The patent transitions from sequential single-word processing to parallel multi-word processing by organizing sub-word FSMs to handle different bit segments simultaneously. This dimensional shift from serial to parallel processing architecture enables the system to evaluate multiple potential pattern matches at once, dramatically improving search throughput
2Productivity
If the FSM word size is increased to process multiple words at each state update, then the search time is reduced, but the memory requirements increase exponentially
Solution Approach 1:
The patent segments the large N-bit input word into multiple smaller sub-words, each processed by a dedicated sub-word FSM. This segmentation allows the system to maintain smaller, more manageable memory structures for each sub-FSM while achieving parallel processing of the entire N-bit word, thus reducing overall memory requirements compared to a single large FSM
Solution Approach 2:
The patent combines the results from multiple sub-word FSMs using a combiner circuit that integrates their outputs to determine if a complete pattern match has occurred. This merging approach allows the system to achieve the functionality of processing large words while using only the memory resources required for smaller sub-words, effectively decoupling processing capability from memory consumption
3Productivity
If parallel FSMs are used to improve processing speed, then the search throughput increases, but the implementation is limited to fixed patterns and cannot handle variable patterns
Solution Approach 1:
The patent designs sub-word FSMs with universal state representations that can accommodate both fixed and variable patterns. Each sub-FSM maintains states that represent partial matches of variable-length patterns, and the combiner integrates these states to recognize complete patterns of variable length. This universal design allows the same parallel architecture to handle both fixed patterns and variable patterns effectively
Data Source
AI summary
An apparatus that searches an input stream having a sequence of N-bit wide data words for a pattern using a plurality of small FSMs is disclosed. The apparatus includes a plurality of sub-word FSMs and a combiner. Each sub-word FSM has an input word size less than N-bits. Each FSM processes a corresponding segment of the N-bit words and generates a match output indicative of a possible match to the pattern when one of the input words to that FSM is received and that FSM moves to a predetermined match state. The combiner receives the match outputs from all of the sub-word FSMs and generates a pattern match output if all of the sub-word FSMs indicate a match to the pattern. The pattern is a variable pattern. In one embodiment, the FSMs are single bit FSMs.