Sub-Word Line Driver Layout for Faster DRAM Signal Setup
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Solution Overview
Problem
Memory devices, particularly DRAMs, face challenges with slow signal setup speeds of word lines and bit lines, which affect operation timing and data reliability due to complex wiring structures and load factors, leading to reduced timing margins and performance.
Innovation Solution
The memory device incorporates a core peripheral circuit structure with sub-word line driver circuits and sense amplifier circuits that overlap memory blocks in a specific direction, including even and odd sub-arrays, to enhance signal setup speeds by optimizing connections to word lines and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device size is increased for higher capacity and integration, then storage capacity improves, but signal setup speed of word lines and bit lines deteriorates
Solution Approach 1:
The memory device is divided into a core peripheral circuit structure and a cell array structure that are physically separated and vertically stacked. The core peripheral circuit structure contains the row decoder and sense amplifier circuits, while the cell array structure contains the memory cell array. This segmentation allows independent optimization of each structure, enabling high-speed signal processing in the peripheral circuits while maintaining large storage capacity in the cell array.
Solution Approach 2:
The patent transitions from a planar configuration to a three-dimensional stacked configuration. The core peripheral circuit structure and cell array structure are positioned at different vertical levels and connected through bonding metal pads. This dimensional change reduces the horizontal wiring distance for signal connections, thereby improving signal setup speed while preserving large storage capacity through vertical stacking.
2Adaptability or versatility
If wiring structures become more complex for higher integration, then device functionality improves, but signal setup speed deteriorates
Solution Approach 1:
The complex wiring structures are segmented by separating the row decoder and sense amplifier circuits into a distinct core peripheral circuit structure. This segmentation simplifies the wiring within each structure while maintaining overall device functionality, and the vertical stacking reduces the total wiring length required for signal transmission.
Solution Approach 2:
Bonding metal pads are introduced as intermediary connection elements between the core peripheral circuit structure and the cell array structure. These bonding pads provide direct electrical connections that simplify the wiring path for signals traveling between the row decoder and memory cell array, thereby improving signal setup speed while preserving device functionality.
Data Source
AI summary
A memory device includes a core peripheral circuit structure and a cell array structure. The cell array structure includes a first sub-array and a second sub-array. The core peripheral circuit structure includes first and second even sub-word line driver circuit and first and second odd sub-word line driver circuits. A first area of the core peripheral circuit structure at least partially overlaps the first sub-array and includes the first even sub-word line driver circuit and the first odd sub-word line driver circuit. A second area of the core peripheral circuit structure at least partially overlaps the second sub-array and includes the second even sub-word line driver circuit and the second odd sub-word line driver circuit.