Sub-word-line driver voltage stability and interference reduction
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Solution Overview
Problem
The increasing demand for high-performance semiconductor memory devices requires improving the capacity and speed of DRAM, which is hindered by speed delays in applying voltage to word lines connected with many memory cells, necessitating the division of word lines into sub-word lines and the use of sub-word line drivers to address these issues.
Innovation Solution
The semiconductor memory device incorporates a sub-word-line driver configuration with a word line pull-up transistor, a pull-down transistor, and a keeping transistor, along with parasitic transistors, to maintain stable voltage levels and improve endurance to high voltages, using a peripheral active region with specific impurity regions and gate electrodes to efficiently drive sub-word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells connected to one word line is increased to increase capacity, then the capacity of the DRAM is improved, but the speed delay issue occurs when applying word line voltage
Solution Approach 1:
The patent divides a single word line into multiple sub-word lines (first sub-word line and second sub-word line) and uses separate sub-word line drivers for each segment. This segmentation allows each driver to control fewer memory cells independently, reducing the voltage application delay while maintaining the ability to address a larger total number of memory cells through coordinated operation of multiple drivers.
2Speed
If sub-word line drivers are used to reduce voltage application delay, then the speed is improved, but the device complexity increases due to additional transistors and interconnections
Solution Approach 1:
The patent combines multiple functions into shared components: the first and second keeping transistors share a common source region, and the first and second pull-down transistors share a common voltage supply through the parasitic transistor. This merging approach reduces the total number of discrete components and interconnections compared to completely separate driver circuits, thereby reducing device complexity while maintaining the speed benefits of multiple sub-word line drivers.
Solution Approach 2:
The parasitic transistor serves multiple functions: it supplies the first voltage to both the first pull-down transistor and the second pull-down transistor, and it enables voltage sharing between the two sub-word line drivers. This multi-functionality reduces the need for separate voltage supply paths and components, simplifying the overall driver structure.
3Quantity of substance
If the distance between word lines is reduced to increase capacity, then the integration density is improved, but the interference between interconnection lines increases
Solution Approach 1:
By segmenting the word line control into multiple sub-word lines with dedicated drivers, the patent enables more precise and localized voltage application. This segmentation allows for better spatial distribution of signaling activity, reducing the duration and intensity of voltage transitions on any single word line, thereby minimizing capacitive coupling and crosstalk interference between closely-spaced interconnection lines.
Data Source
AI summary
A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.