Successive Approximation ADC Layout With Fewer Comparators

Solution Overview

Problem

Conventional analog to digital converters (ADCs) based on flash-type architectures have high current consumption and require a large layout area due to the number of comparators needed, making them unsuitable for mobile devices.

Innovation Solution

An analog to digital converter using a successive approximation algorithm (SAA) with a reduced number of comparators, implemented with a reference voltage generating unit, a reference voltage selecting unit, and a digital signal output unit, which includes transfer gates and decoders to selectively transfer and compare reference voltages with an analog input signal, thereby reducing the number of comparators and improving layout efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional flash-type ADC uses multiple comparators to achieve fast conversion speed, then the processing speed is improved, but the current consumption and layout area increase proportionally

Engineering Contradiction:

Improveconversion speedVSAvoidcurrent consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent segments the conversion process into multiple stages: a coarse conversion stage using fewer comparators to generate initial digital values, and a fine conversion stage using Successive Approximation Algorithm (SAA) to refine the digital output. This segmentation allows the system to achieve fast initial conversion while reducing the total number of comparators needed, thereby lowering current consumption while maintaining overall conversion speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the operation mode of the ADC by selectively activating different conversion modes (coarse conversion vs. fine conversion) based on the input signal characteristics. The system can switch between using multiple comparators for fast conversion and using fewer comparators with SAA for power-efficient conversion, making the current consumption adaptive rather than static.

Inventive Principle:

Principle #15Dynamics

2Speed

If a conventional flash-type ADC uses multiple comparators to achieve fast conversion speed, then the processing speed is improved, but the layout area increases proportionally

Engineering Contradiction:

Improveconversion speedVSAvoidlayout area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The patent segments the conversion process into multiple stages: a coarse conversion stage using fewer comparators to generate initial digital values, and a fine conversion stage using Successive Approximation Algorithm (SAA) to refine the digital output. This segmentation allows the system to achieve fast initial conversion while reducing the total number of comparators needed, thereby lowering current consumption while maintaining overall conversion speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts the operation mode of the ADC by selectively activating different conversion modes (coarse conversion vs. fine conversion) based on the input signal characteristics. The system can switch between using multiple comparators for fast conversion and using fewer comparators with SAA for power-efficient conversion, making the current consumption adaptive rather than static.

Inventive Principle:

Principle #15Dynamics

3Measurement precision

If a conventional ADC uses many comparators to handle all reference voltages, then the measurement precision is improved, but the device complexity increases

Engineering Contradiction:

Improveconversion precisionVSAvoidnumber of comparators

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the conversion process into multiple stages: a coarse conversion stage using fewer comparators to generate initial digital values, and a fine conversion stage using Successive Approximation Algorithm (SAA) to refine the digital output. This segmentation allows the system to achieve fast initial conversion while reducing the total number of comparators needed, thereby lowering current consumption while maintaining overall conversion speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements feedback mechanisms where the digital values generated in the coarse conversion stage are fed back into the SAA process. The SAA uses this initial digital information along with feedback from the comparators to iteratively refine the digital output, achieving high precision without requiring a full set of comparators for all reference voltages simultaneously.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS7893857B2Analog to digital converter using successive approximation

Publication Date: 2011.02.22 MIMIRIP LLC

AI summary

Disclosed is a flash analog to digital converter (ADC) capable of reducing area requirements and using successive approximation. The ADC includes a reference voltage generating unit receiving an external voltage and outputting M reference voltages. A reference voltage selecting unit outputs N reference voltages less than the number of the voltages outputted by the reference voltage generating unit according to a supplied control signal. A digital signal output unit compares the N reference voltages outputted by the reference voltage selecting unit with an external analog input signal and outputs the comparison result as an N-bit digital signal.