Successive Approximation A/D Converter Power Reduction
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Solution Overview
Problem
Conventional successive approximation type A/D converters experience high current consumption due to through current in buffering circuits and continuous current flow in reference voltage generating circuits, especially when operated at low frequencies, leading to increased power consumption.
Innovation Solution
Incorporating a buffering control circuit that blocks power supply to the buffering circuit during the sampling period and using tri-state inverters or selecting between high and low performance buffering circuits based on clock frequency to minimize current consumption, along with a circuit to stop unnecessary reference voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buffering circuit operates continuously to buffer the comparator output, then the output signal is always available, but current consumption increases due to through current during sampling period
Solution Approach 1:
The buffering circuit is controlled to operate periodically rather than continuously. The control circuit enables the buffering circuit only during the successive comparison period when the comparator output needs to be buffered, and disables it during the sampling period when the comparator output is not valid. This periodic operation eliminates through current while ensuring output signal availability when needed.
2Reliability
If the reference voltage generating circuit operates continuously to provide reference voltage, then the reference voltage is always available for comparison, but current consumption increases
Solution Approach 1:
The reference voltage generating circuit is controlled to operate periodically, generating reference voltage only during the successive comparison period when it is needed for comparison operations. The circuit is disabled during the sampling period, eliminating continuous current consumption while ensuring reference voltage availability when required.
3Speed
If high-performance buffering circuit is used to ensure fast signal transmission, then conversion speed is improved, but current consumption increases especially at low clock frequencies
Solution Approach 1:
The buffering circuit's performance characteristics are dynamically adjusted based on operating conditions. The control circuit modifies the buffering circuit's operation according to the clock frequency, enabling high-performance mode when fast conversion is needed and reducing performance (and current consumption) when operating at lower frequencies, thus optimizing the trade-off between speed and power consumption.
Data Source
AI summary
An A/D converter of an successive approximation type according to the present invention comprises a sample hold circuit, a reference voltage generating circuit, a comparator for comparing the reference voltage generated by the reference voltage generating circuit to a value of the input analog signal retained in the sample hold circuit, a control circuit for successively controlling the reference voltage generating circuit so that a value of the reference voltage approximates to the value of the input analog signal retained in the sample hold circuit, a buffering circuit for outputting an output value corresponding to an output voltage of the comparator, a latch circuit for retaining the output value of the buffering circuit corresponding to the output value of the comparator per bit as a digital value, and a buffering control circuit for blocking a power supply to the buffering circuit during the sampling period is provided.