Successive Time-to-Digital Conversion for Low-Power DPLL Phase Error Sensing
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face challenges in achieving fine resolution error signals with low power consumption, as high-resolution time-to-digital converters (TDCs) require significant power and IC die area, making them unattractive compared to conventional charge pump architectures.
Innovation Solution
The Successive Time-to-Digital Converter (STDC) system reduces power consumption by achieving comparable resolution with almost an order of magnitude fewer delay elements/samplers, allowing for dynamic power management and eliminating the need for a divider in the feedback loop, thereby improving the performance-to-power dissipation ratio of TDCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-resolution TDC is used to achieve fine resolution error signals, then measurement precision is improved, but power consumption increases significantly
Solution Approach 1:
The TDC is divided into multiple stages: a first TDC that operates continuously to track phase differences, and a second TDC that is activated only when phase offset exceeds a threshold. This segmentation allows the system to maintain measurement precision when needed while reducing power consumption during normal operation.
Solution Approach 2:
The system dynamically adjusts the operation of the second TDC based on the phase offset condition. When the phase offset exceeds the threshold, the second TDC is activated to provide fine resolution measurement; otherwise, it remains inactive. This dynamic operation optimizes the balance between resolution and power consumption.
2Measurement precision
If a high-resolution TDC is used to achieve fine resolution error signals, then measurement precision is improved, but IC die area increases
Solution Approach 1:
The TDC functionality is segmented between two separate TDCs with different resolution capabilities. The first TDC handles coarse measurement continuously, while the second TDC provides fine resolution only when necessary. This segmentation reduces the total number of delay elements and samplers needed compared to a single high-resolution TDC.
Solution Approach 2:
The second high-resolution TDC is designed as a resource that is not continuously active but only deployed when phase offset exceeds the threshold. This approach allows the system to have fine resolution capability without permanently allocating the large IC die area required for a continuously operating high-resolution TDC.
3Use of energy by moving object
If dynamic power management is implemented in the TDC, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The system uses feedback from the phase offset measurement to control the activation of the second TDC. When the phase offset exceeds the threshold, the feedback signal activates the second TDC; otherwise, it remains inactive. This feedback-based control achieves dynamic power management with relatively simple logic.
Solution Approach 2:
The TDC system automatically adjusts its own power consumption based on the phase offset condition without requiring external control. The first TDC continuously monitors the phase difference and automatically triggers the second TDC when needed, enabling self-service power management.
Data Source
AI summary
A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.