Multiplexed Sum-of-Products Circuit Area Reduction
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Solution Overview
Problem
Existing datapath synthesis methods cannot fully exploit optimal sum-of-products (SOP) and product-of-sums (POS) expressions due to non-SOP expressions and muxing/shifting within SOPs, limiting efficient merging and area reduction in integrated circuits.
Innovation Solution
A method to transform a set of mutually-exclusive SOPs into a single equivalent SOP using a binary linear program (BLP) to minimize multiplexing and negate negative terms, resulting in a hardware circuit design with reduced multiplexing and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple multiplexed sum-of-products functions are implemented separately, then each function can be selected independently, but the amount of multiplexing and area required increases
Solution Approach 1:
The patent merges multiple multiplexed sum-of-products functions into a single unified sum-of-products function. By aligning elements and combining the functions, the patent reduces the amount of multiplexing required while maintaining the ability to select between different functions. This merging approach directly reduces the circuit area needed to implement the same functionality.
Solution Approach 2:
The patent creates a single sum-of-products function that can perform multiple functions through strategic alignment of elements and use of shared resources. The unified function structure allows different sum-of-products operations to be executed by the same hardware, reducing area while preserving adaptability.
2Area of stationary object
If elements are aligned to reduce multiplexing, then area is reduced, but the complexity of rearranging and merging increases
Solution Approach 1:
The patent applies preliminary action by pre-aligning the elements of the sum-of-products functions before merging. This alignment step is performed systematically to facilitate the subsequent merging process, reducing the complexity of the overall transformation. The elements are arranged in a specific order that simplifies the combination process.
Solution Approach 2:
The patent segments the multiple sum-of-products functions into individual components that can be independently aligned and then systematically merged. By breaking down the functions into manageable elements, the patent reduces the overall complexity of the rearranging and merging process while achieving area reduction.
Data Source
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AI summary
A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c,... ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions comprises aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions. Additionally, negative terms in the sum-of-products functions are selectively negated so that particular products are always positive.