Super Block Allocation for Flash Memory Write Efficiency
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Solution Overview
Problem
Existing electronic devices face inefficiencies in data storage and management due to limitations in addressing and block allocation strategies, leading to suboptimal performance in handling write requests and maintaining data integrity in nonvolatile memory systems.
Innovation Solution
The implementation of a controller that groups memory blocks into super blocks, manages opened and closed super blocks, and allocates logical address ranges to efficiently write data, ensuring that write requests are handled by either special or normal super blocks based on availability, thereby optimizing data storage and reducing garbage collection and wear leveling operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory blocks are grouped into super blocks with traditional addressing strategies, then data storage capacity is maintained, but write efficiency deteriorates and invalid data concentration increases
Solution Approach 1:
The patent segments the address space into multiple logical address ranges, each mapped to specific super blocks. This segmentation allows the controller to selectively manage write operations to different super blocks based on their state (opened/closed), thereby improving write efficiency and reducing invalid data concentration in any single super block.
Solution Approach 2:
The patent performs preliminary actions by pre-opening multiple super blocks and pre-mapping logical address ranges to them before write operations occur. This allows the controller to immediately direct writes to appropriate super blocks without needing to close and reopen blocks during operation, thus improving write efficiency and preventing invalid data accumulation.
2Productivity
If traditional block allocation strategies are used, then memory structure simplicity is maintained, but data storage efficiency and device lifespan deteriorate
Solution Approach 1:
The patent introduces a new dimension of management by implementing a two-level mapping structure: logical address ranges mapped to super blocks, and super blocks mapped to physical memory blocks. This dimensional approach enables more efficient data storage and device lifespan management while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent implements dynamic super block management where super blocks can be opened and closed based on write operation requirements. The controller dynamically selects which super block to write to based on the logical address range and the current state of super blocks, enabling adaptive optimization of storage efficiency and device lifespan without excessive complexity.
3Adaptability or versatility
If super blocks are opened and closed frequently, then address mapping flexibility is improved, but operational overhead and performance deterioration increase
Solution Approach 1:
The patent performs preliminary actions by pre-opening multiple super blocks and establishing logical address range mappings before write operations are needed. This preliminary setup reduces the need for frequent open/close operations during normal writing, thereby maintaining address mapping flexibility while reducing operational overhead and performance impact.
Data Source
AI summary
An electronic device includes a controller; and a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to execute processes. The non-transitory computer-readable storage medium includes a plurality of memory blocks. The processes include grouping the plurality of memory blocks into a plurality of super blocks; selecting a first super block among the plurality of super blocks depending on one or more logical addresses corresponding to write-requested data, and writing the data; and mapping the first super block to a first logical address range. The first logical address range is configured by successive addresses corresponding to a super block size, and a start address of the successive addresses is a start logical address of the one or more logical addresses.