Super CMOS Logic With Schottky Diodes for Sub-1.8V IC Scaling
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Solution Overview
Problem
Conventional CMOS technology faces challenges in reducing physical dimensions and power supply voltage while maintaining performance and cost efficiency, leading to limitations in further miniaturization and increased device functionality, especially below 1.8V, which hinders the advancement of IC density and solar energy conversion efficiency.
Innovation Solution
The introduction of Super CMOS (SCMOS) technology, which incorporates Schottky CMOS Logic (SCL) and Schottky pass transistor logic (SPTL) with low barrier Schottky diodes, dynamic logic circuits, and multi-level cell (MLC) transistors, enabling compact, high-speed, and low-power designs that support single voltage supplies down to 0.7V, reducing transistor counts and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS technology is used to reduce physical dimensions and power supply voltage, then IC density and device functionality are improved, but performance and cost efficiency deteriorate below 1.8V
Solution Approach 1:
The patent changes the fundamental parameters of CMOS technology by introducing Schottky barrier diodes with optimized barrier heights and integrating them with transistor structures. This modifies the electrical characteristics to enable operation at lower voltages while maintaining performance, directly resolving the contradiction between miniaturization and performance retention below 1.8V
Solution Approach 2:
The patent creates composite semiconductor structures by integrating Schottky barrier diodes with CMOS transistors, forming hybrid devices that combine the advantages of both technologies. This composite approach enables lower voltage operation with maintained performance, addressing the contradiction between reduced dimensions and performance efficiency
2Area of stationary object
If physical dimensions of circuit elements are reduced to increase IC density, then manufacturing cost is reduced, but device functionality and performance are compromised
Solution Approach 1:
The patent transitions from planar device structures to vertically integrated three-dimensional architectures by stacking Schottky barrier diodes with transistors. This dimensional change enables increased functionality and performance within reduced footprint areas, resolving the contradiction between chip area reduction and device functionality maintenance
3Use of energy by moving object
If power supply voltage is reduced below 1.8V to save power, then energy consumption is reduced, but speed degradation occurs
Solution Approach 1:
The patent modifies the voltage-current characteristics by integrating Schottky barrier diodes with transistors, creating devices that maintain higher switching speeds at reduced voltages. The optimized barrier heights and device geometries enable efficient operation below 1.8V without significant speed degradation, resolving the energy-speed tradeoff
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
SCMOS technology achieves significant power savings, compact integration, and improved performance by reducing transistor counts, gate counts, and wiring distances, enabling efficient solar energy conversion and supporting high-speed, low-power applications across various microelectronics systems.
Implementation Method 1
incorporates Schottky CMOS Logic (SCL) and Schottky pass transistor logic (SPTL) with low barrier Schottky diodes
Data Source
AI summary
A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.