Super Home Node Cache Coherency with Compact Snoop Filters
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Solution Overview
Problem
In large multi-chip data processing systems, tracking the presence of cache lines across numerous caching agents becomes impractical due to the large size of snoop filter tables, leading to inefficiencies and increased latency, especially when managing cache coherency across multiple chips.
Innovation Solution
Implementing a Super Home Node (HNS) that combines the functions of a local coherency node and home node, allowing each remote integrated circuit to present as a single caching agent, reducing the need for extensive snoop filter tracking and enabling local management of cache coherency, thereby optimizing cache hierarchy and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a snoop filter table stores an entry for each cache line with multi-bit device identifiers for each caching agent, then cache coherency tracking is accurate, but the snoop filter table becomes too large for large scale systems
Solution Approach 1:
The patent segments the snoop filter table into multiple smaller tables, each tracking cache lines for a subset of caching agents. This allows accurate tracking to be maintained while keeping individual table sizes manageable. The segmented tables are organized hierarchically with different levels of granularity.
Solution Approach 2:
The patent introduces a hierarchical dimension to the snoop filter structure, organizing caching agents into groups or clusters. Instead of a flat structure where every agent is tracked individually in one large table, the hierarchical organization creates multiple levels of tracking, reducing the width of presence vectors needed in each table entry.
2Reliability
If a presence vector is used for each caching agent in the snoop filter table, then cache line presence tracking is comprehensive, but the memory requirements become impractical for 512 caching agents
Solution Approach 1:
The presence vector is segmented across multiple snoop filter tables rather than being stored as a single 512-bit vector in one table. Each table stores a portion of the tracking information, reducing the memory burden on any single table while maintaining comprehensive tracking capability across the entire system.
Solution Approach 2:
The patent transforms the problem from storing wide presence vectors in a single dimension (one large table) to storing narrower vectors across multiple dimensions (multiple smaller tables organized hierarchically). This dimensional transformation reduces the memory requirements at any given location while preserving overall tracking completeness.
3Reliability
If extensive snoop filter tracking is implemented across all caching agents, then cache coherency is accurately maintained, but system latency increases
Solution Approach 1:
By segmenting the snoop filter into smaller tables, the patent enables more efficient cache line lookups and coherency checks. The segmented structure allows the system to quickly determine which subset of caching agents may have a cache line without scanning through all 512 agents, thereby reducing latency while maintaining accurate coherency tracking.
Solution Approach 2:
The hierarchical organization introduces a dimensional structure that enables faster coherency checking. Instead of a linear scan through all caching agents, the hierarchical structure allows the system to navigate through organized groups, reducing the time required to maintain and check cache coherency across the system.
Data Source
AI summary
A super home node of a first chip of a multi-chip data processing system manages coherence for both local and remote cache lines accessed by local caching agents and local cache lines accessed by caching agents of one or more second chips. Both local and remote cache lines are stored in a shared cache, and requests are stored in shared point-of-coherency queue. An entry in a snoop filter table of the super home node includes a presence vector that indicates the presence of a remote cache line at specific caching agents of the first chip or the presence of a local cache line at specific caching agents of the first chip and any caching agent of the second chip. All caching agents of the second chip are represented as a single caching agent in the presence vector.