Super Junction Column Layout Tolerant to Layer Misalignment
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices with repeating layers, such as super junction layers, is that positional deviations between lower and upper layers can lead to the formation of narrow portions at the boundary surface, which deteriorate the electrical characteristics due to the large aspect ratio of n-type and p-type columns, making it difficult to collectively form thick layers without compromising on-resistance and breakdown voltage.
Innovation Solution
A method is introduced where the lower and upper portions of the conductivity columns in the repeating layer are alternately arranged, with the end portions having a smaller width at the boundary surface than the central portions, allowing for wider connection areas between the layers, thereby mitigating the impact of positional deviations and maintaining electrical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick repeating layers are formed to reduce on-resistance, then electrical conductivity improves, but positional deviations between layers cause narrow portions at boundary surfaces that deteriorate breakdown voltage
Solution Approach 1:
The patent applies local quality by creating a tapered structure where the width of the second conductivity type column gradually decreases from the central portion toward the end portion at the boundary surface. This localized geometric modification ensures that even if positional deviations occur between lower and upper layers, the tapered end portions prevent the formation of narrow portions, thereby maintaining breakdown voltage without compromising the overall layer thickness needed for low on-resistance.
2Reliability
If n-type column width is reduced to lower on-resistance, then electrical conductivity improves, but the aspect ratio increases making the device more sensitive to positional deviations
Solution Approach 1:
The patent employs asymmetry by creating columns with different width profiles: the first conductivity type column maintains a uniform width, while the second conductivity type column has a tapered profile with wider central portions and narrower end portions. This asymmetric design allows the device to accommodate the high aspect ratio of narrow columns while the tapered geometry provides tolerance against positional deviations, enabling reduced on-resistance without excessive sensitivity to alignment errors.
3Reliability
If layer thickness is increased to improve electrical characteristics, then device performance improves, but manufacturing difficulty increases due to alignment sensitivity
Solution Approach 1:
The patent applies preliminary action by pre-forming the tapered structure of the second conductivity type column before depositing the upper repeating layer. The tapered end portions are created in advance during the lower layer formation, which provides built-in tolerance for subsequent layer alignment. This preliminary geometric preparation reduces the sensitivity to positional deviations during upper layer deposition, enabling thicker layers to be manufactured with maintained electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures robustness against positional deviations, suppressing the deterioration of electrical characteristics and maintaining the trade-off between low on-resistance and high breakdown voltage, particularly beneficial for semiconductor devices like MOSFETs and IGBTs, especially when the n-type column width is less than 1.0 μm.
Implementation Method 1
forming a lower layer of the repeating layer in which a lower portion of a first conductivity column and a lower portion of a second conductivity column are alternately arranged in the repeating direction by replacing a lower epitaxial layer for the first conductivity column with a region for the second conductivity column
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming a lower layer of a repeating layer in which a first conductivity column and a second conductivity column are alternately arranged in a repeating direction by replacing a lower epitaxial layer for the first conductivity column with a region for the second conductivity column; and forming an upper layer of the repeating layer by replacing an upper epitaxial layer for the first conductivity column with a region for the second conductivity column. The second conductivity column includes a central portion and an end portion between the central portion and a boundary surface of the lower layer and the upper layer. A width of the end portion in the repeating direction is smaller than that of the central portion.