Super Junction Semiconductor Device Drift Region Resistance Reduction
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Solution Overview
Problem
Conventional super junction semiconductor devices face challenges in achieving low resistance in the drift region near the drain due to higher resistance compared to the source region, limiting high current density during operation.
Innovation Solution
The design includes an n-type semiconductor region with p-type semiconductor regions alternately disposed, where the n-type ion implantation region is formed at the lower end, reducing the depletion region size and increasing the n-type charge concentration, and the p-type doping concentration is higher at the lower end to balance charges and form a critical electric field, thereby reducing drain and source resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional super junction structure is used with p-type pillar regions formed in an n-type epitaxial region, then breakdown voltage is improved due to depletion layer extension in both vertical and horizontal directions, but resistance in the drift region near the drain region becomes relatively higher, limiting current density
Solution Approach 1:
The patent applies local quality by creating an n-type ion implantation region specifically at the lower end of the n-type semiconductor region where the drift region is located. This localized modification increases the n-type charge concentration precisely in the area where resistance is problematic, without altering the overall super junction structure that provides the breakdown voltage. The selective doping approach allows different regions to have optimized properties for their specific functions.
Solution Approach 2:
The patent changes the doping concentration parameter by forming an n-type ion implantation region with higher n-type charge concentration at the lower end of the n-type semiconductor region. This parameter change directly addresses the resistance issue in the drift region near the drain, while the balanced charge design maintains the breakdown voltage characteristics.
2Reliability
If the n-type and p-type regions are designed with balanced charge quantities for optimal breakdown voltage, then high breakdown voltage is achieved, but the resistance of the drift region near the drain remains relatively higher compared to the source region
Solution Approach 1:
The patent introduces a localized n-type ion implantation region at the lower end of the n-type semiconductor region, creating a specific area with enhanced n-type charge concentration. This local modification reduces resistance in the drift region near the drain without disrupting the overall charge balance between n-type and p-type regions, thereby maintaining breakdown voltage while reducing energy loss.
Solution Approach 2:
The n-type ion implantation region is formed in advance during the manufacturing process, specifically at the lower end of the n-type semiconductor region. This preliminary action of selective doping prepares the drift region with higher charge concentration before device operation, ensuring low resistance characteristics from the start while maintaining the charge-balanced super junction structure for optimal breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases drain and source resistance, enhances current density, and stabilizes the breakdown voltage, allowing for efficient current flow and increased internal pressure against reverse current.
Implementation Method 1
an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions
Implementation Method 2
In a super junction semiconductor device, a depletion layer extends in both a vertical direction and a horizontal direction when a voltage is applied to its drain
Implementation Method 3
Since charge does not exist in the vertical direction, an electric field in the vertical direction is constantly generated in theory
Data Source
AI summary
There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.