Super Junction FET Avalanche Ruggedness via Edge Area Confinement
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Solution Overview
Problem
Super junction FETs face challenges in achieving improved avalanche ruggedness, particularly in unclamped inductive switching environments where process-induced inhomogeneities can lead to localized thermal stress and device degradation.
Innovation Solution
The super junction semiconductor device is designed with a structure that includes areas of different conductivity types, where a second portion with a lower nominal breakdown voltage is defined to concentrate the avalanche effect, dispersing thermal stress and improving ruggedness by ensuring uniform heat dissipation and reduced process inhomogeneities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the super junction structure uses high impurity concentrations to achieve low on-state resistance, then the on-state resistance is reduced, but the reverse breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating different compensation ratios in different regions of the super junction structure. The cell area maintains a first compensation ratio optimized for low on-state resistance, while the edge area has a second compensation ratio that provides higher reverse breakdown voltage. This spatial variation in compensation ratio allows each region to be optimized for its specific function, resolving the contradiction between low on-state resistance and high avalanche ruggedness.
Solution Approach 2:
The super junction structure is segmented into distinct regions: a cell area with first compensation ratio and an edge area with second compensation ratio. This segmentation allows the device to handle different electrical stresses in different locations, confining avalanche breakdown to the edge area while maintaining high performance in the cell area, thereby improving avalanche ruggedness without compromising on-state resistance.
2Reliability
If the super junction structure has uniform compensation ratio throughout, then manufacturing is simplified, but process inhomogeneities cause localized thermal stress and reduced avalanche ruggedness
Solution Approach 1:
Instead of requiring uniform compensation ratio throughout the entire structure, the patent deliberately creates local quality variations by implementing different compensation ratios in the cell area versus the edge area. This approach actually reduces the impact of process inhomogeneities by providing a buffer zone in the edge area where avalanche breakdown can occur without affecting the critical cell area, thereby improving reliability while maintaining manufacturability.
3Speed
If the device operates in unclamped inductive switching environment, then switching speed is improved, but avalanche breakdown causes device degradation
Solution Approach 1:
The patent converts the harmful avalanche breakdown effect into a beneficial controlled phenomenon by designing the edge area with higher compensation ratio to specifically attract and confine avalanche breakdown. This allows unclamped inductive switching to operate at high speeds while the avalanche effect is contained in the edge area, preventing device degradation in the critical cell area and improving overall reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively enhances avalanche ruggedness by confining the avalanche breakdown to a specific area with uniform geometry and impurity distributions, reducing the risk of device degradation and improving reliability.
Implementation Method 1
In the reverse mode depletion zones extend between the p-doped and n-doped areas in a lateral direction such that super junction FETs accommodate a high reverse breakdown voltage
Implementation Method 2
The induced current triggers an avalanche mechanism in the FET, wherein the electric field in the FET generates mobile charge carriers conveying the off-state current
Data Source
AI summary
A super junction semiconductor device includes a super junction structure that is formed in a semiconductor body having a first and a second, parallel surface. The super junction structure includes first areas of the first conductivity type and second areas of a second conductivity type which is the opposite of the first conductivity type. In a cell area surrounded by an edge area, the super junction structure has a first nominal breakdown voltage in a first portion and a second nominal breakdown voltage, which differs from the first nominal breakdown voltage, in a second portion to provide improved avalanche ruggedness.


