Semiconductor Super-Junction Gate Alignment via Self-Service
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Solution Overview
Problem
The high cost and risk associated with the photoetching process in manufacturing semiconductor super-junction devices due to its high cost and alignment deviation issues.
Innovation Solution
A method that involves forming a hard mask layer on an n-type epitaxial layer, defining the position of a p-type column through photoetching, etching the hard mask layer to create a first trench with a wider opening, forming a gate in the trench, and then using the hard mask layer and insulating side walls to create a second trench, allowing the p-type column to be formed in self-alignment, thus reducing the need for multiple photoetching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the photoetching process is performed multiple times to form the p-type column and gate, then the manufacturing precision can be improved, but the manufacturing cost increases and the risk of alignment deviation increases
Solution Approach 1:
The gate structure serves as its own alignment reference for forming the p-type column. The insulating side wall formed on the gate automatically provides the positioning boundary, eliminating the need for separate photoetching alignment processes. The system uses itself as the reference, achieving self-alignment that reduces both cost and alignment risk.
Solution Approach 2:
The gate and insulating side wall are formed in advance before the p-type column formation. This preliminary structuring creates the alignment reference beforehand, so that when the p-type column is subsequently formed, the position is automatically determined by the pre-existing gate structure, avoiding the need for additional photoetching alignment steps.
2Manufacturing precision
If the photoetching process is performed multiple times to form the p-type column and gate, then the manufacturing precision can be improved, but the manufacturing risk increases
Solution Approach 1:
The gate structure serves as its own alignment reference for forming the p-type column. The insulating side wall formed on the gate automatically provides the positioning boundary, eliminating the need for separate photoetching alignment processes. The system uses itself as the reference, achieving self-alignment that reduces both cost and alignment risk.
Solution Approach 2:
The gate and insulating side wall are formed in advance before the p-type column formation. This preliminary structuring creates the alignment reference beforehand, so that when the p-type column is subsequently formed, the position is automatically determined by the pre-existing gate structure, avoiding the need for additional photoetching alignment steps.
3Manufacturing precision
If multiple photoetching processes are used to form the gate and p-type column, then the manufacturing precision can be improved, but the productivity decreases
Solution Approach 1:
The formation of the gate and the p-type column positioning are merged into a single integrated process sequence. The gate formation process simultaneously creates the structural element and the alignment reference for the p-type column, combining what would traditionally require separate photoetching steps into one unified manufacturing flow.
Solution Approach 2:
The gate structure serves as its own alignment reference for forming the p-type column. The insulating side wall formed on the gate automatically provides the positioning boundary, eliminating the need for separate photoetching alignment processes. The system uses itself as the reference, achieving self-alignment that reduces both cost and alignment risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces the manufacturing cost and risk of semiconductor super-junction devices by minimizing the number of photoetching processes required, enhancing the manufacturing efficiency and reliability.
Implementation Method 1
a position of a p-type column is defined through a photoetching process, then the hard mask layer is etched
Implementation Method 2
The n-type epitaxial layer is etched with the hard mask layer as a mask, and a first trench is formed in the n-type epitaxial layer
Implementation Method 3
a first conductive layer is deposited, and the first conductive layer is etched back so as to form a gate in the gate region of the first trench
Implementation Method 4
An insulating side wall is formed on an exposed side wall of the gate
Implementation Method 5
the n-type epitaxial layer is etched with the hard mask layer and the insulating side wall as masks, and forming a second trench in the n-type epitaxial layer
Implementation Method 6
The p-type column is formed in the p-type column region and the second trench
Data Source
AI summary
Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.