Power Semiconductor Super Junction Impurity Profile
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Solution Overview
Problem
Power semiconductor devices face a tradeoff between on-resistance and breakdown voltage, with existing super junction structures requiring increased impurity differences to maintain breakdown voltage, leading to increased on-resistance due to process variations.
Innovation Solution
A power semiconductor device with a super junction structure where the sum of impurities in the n-pillar and p-pillar layers decreases at the ends, reducing the electric field and stabilizing breakdown voltage, while maintaining a balanced impurity distribution to minimize on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amount of impurities in the p-pillar layer and n-pillar layer are made equal to achieve low on-resistance, then the breakdown voltage decreases due to process variation, but if the amount of impurities is increased to compensate, then the on-resistance increases
Solution Approach 1:
The patent applies local quality by creating different impurity concentration profiles in different regions of the pillar layers. Specifically, the impurity concentration is made higher at the center region and lower at the end regions of the pillar layers. This local variation allows the center region to maintain strong electric field for breakdown voltage while the end regions reduce electric field concentration, preventing premature breakdown due to process variation. The local quality principle resolves the contradiction by allowing different impurity amounts in different locations rather than requiring uniform impurity distribution throughout the entire pillar layer.
Solution Approach 2:
The patent employs asymmetry by intentionally creating an asymmetric impurity concentration distribution within the pillar layers. The impurity concentration profile is designed to be symmetric with respect to the center line but asymmetric in magnitude - higher at the center and lower at the ends. This asymmetric distribution pattern allows the structure to tolerate process variations better because the critical center region maintains the necessary impurity level for electric field control, while the end regions have reduced impurity levels that prevent electric field concentration and premature breakdown.
2Reliability
If the difference in impurity amount between p-pillar and n-pillar layers is increased to vary electric field distribution, then breakdown voltage is maintained, but on-resistance increases due to n-pillar layer depletion
Solution Approach 1:
The patent applies local quality by creating different impurity concentration profiles in different regions of the pillar layers. Specifically, the impurity concentration is made higher at the center region and lower at the end regions of the pillar layers. This local variation allows the center region to maintain strong electric field for breakdown voltage while the end regions reduce electric field concentration, preventing premature breakdown due to process variation. The local quality principle resolves the contradiction by allowing different impurity amounts in different locations rather than requiring uniform impurity distribution throughout the entire pillar layer.
Solution Approach 2:
The patent employs asymmetry by intentionally creating an asymmetric impurity concentration distribution within the pillar layers. The impurity concentration profile is designed to be symmetric with respect to the center line but asymmetric in magnitude - higher at the center and lower at the ends. This asymmetric distribution pattern allows the structure to tolerate process variations better because the critical center region maintains the necessary impurity level for electric field control, while the end regions have reduced impurity levels that prevent electric field concentration and premature breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes breakdown voltage and reduces on-resistance by decreasing the electric field at the ends of the pillar layers, enhancing avalanche withstand capability and maintaining a low on-resistance despite process variations.
Implementation Method 1
a non-doped layer is artificially produced by equalizing the amount of charge (amount of impurities) contained in the p-pillar layer with that contained in the n-pillar layer
Implementation Method 2
the impurity concentration profile of the p-pillar layer and the impurity concentration profile of the n-pillar layer are made different from each other... the balance between the amount of impurities in the p-pillar layer and the amount of impurities in the n-pillar layer is locally broken in advance
Implementation Method 3
The dopant concentration that determines the electric resistance of the drift layer cannot exceed a maximum limit, which depends on the breakdown voltage of a pn junction interface
Data Source
AI summary
A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.