Super Junction Semiconductor Layout for On-Resistance Stability
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Solution Overview
Problem
Conventional semiconductor devices with equal gate and p-type column region intervals suffer from variations in on-resistance due to misalignment during manufacturing, leading to increased on-resistance and reduced reliability.
Innovation Solution
A semiconductor device design where the cell pitch differs from the repeat pitch, with a super junction structure formed by alternately repeating p-type and n-type columns, reducing the variation in on-resistance by optimizing the relative positions of repeat regions with respect to gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If p-type column regions are arranged at equal intervals with gate electrodes, then manufacturing is simplified, but misalignment occurs leading to increased on-resistance variation
Solution Approach 1:
The patent applies asymmetry by setting the cell pitch (distance between adjacent gate electrodes) different from the repeat pitch (distance between adjacent p-type column regions). This asymmetric arrangement prevents misalignment between gate electrodes and p-type column regions, eliminating the technical contradiction by ensuring that even when manufactured at equal intervals, the different pitch values prevent direct alignment that would cause resistance variation
2Stability of the object's composition
If cell pitch equals repeat pitch, then structural symmetry is achieved, but misalignment causes increased on-resistance
Solution Approach 1:
The patent deliberately breaks structural symmetry by setting cell pitch different from repeat pitch. This asymmetric design prioritizes reliability by preventing misalignment between gate electrodes and p-type column regions, demonstrating that functional performance takes precedence over geometric symmetry
3Device complexity
If p-type column regions are positioned directly under gate electrodes, then device complexity is reduced, but on-resistance increases due to interference with electron movement
Solution Approach 1:
The asymmetric pitch arrangement automatically positions p-type column regions at offset locations relative to gate electrodes, preventing direct alignment without requiring complex positioning structures. This resolves the contradiction by using pitch differentiation rather than structural complexity to achieve proper spatial relationship
Data Source
AI summary
A semiconductor device includes a substrate, a drift layer of a first conductivity type, a first electrode, a second electrode, a plurality of gate electrodes, and a plurality of repeat regions of a second conductivity type. When center lines respectively passing through centers of the gate electrodes in an arrangement direction of the gate electrodes and extending in a thickness direction of the substrate are defined as cell center lines, a distance between adjacent two of the cell center lines is defined as a cell pitch, center lines respectively passing through centers of the repeat regions in the arrangement direction are defined as repeat center lines, and a distance between adjacent two of the repeat center lines in the arrangement direction is defined as a repeat pitch, the cell pitch is different from the repeat pitch.