Super Junction MISFET Pitch Layout for Breakdown and On-Resistance
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Solution Overview
Problem
Current semiconductor devices with super junction structures face challenges in optimizing both breakdown voltage characteristics and on-resistance, as the inter-column layer pitch and inter-body region pitch significantly influence these parameters, leading to suboptimal performance in MISFET devices.
Innovation Solution
The semiconductor device incorporates a super junction structure with alternately arranged p-type and n-type column layers and body regions, where the inter-body region pitch is adjusted to be shorter than the inter-column layer pitch, allowing for independent optimization of breakdown voltage and on-resistance characteristics through precise pitch control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the inter-column layer pitch and inter-body region pitch are kept equal in conventional super junction structures, then the manufacturing process is simplified, but the breakdown voltage and on-resistance characteristics cannot be independently optimized
Solution Approach 1:
The patent divides the pitch parameters into two independent segments: inter-column layer pitch (P1) and inter-body region pitch (P2). This segmentation allows independent optimization of breakdown voltage (controlled by P1) and on-resistance (controlled by P2), resolving the contradiction between manufacturing simplicity and performance optimization.
Solution Approach 2:
The patent changes the parameter relationship from P1=P2 (conventional) to P1≠P2 (optimized), specifically setting P2<P1. This parameter change enables independent control of electrical characteristics while maintaining manufacturing feasibility through standard photolithography processes.
2Loss of energy
If the inter-body region pitch is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage characteristics deteriorate
Solution Approach 1:
By segmenting the pitch control into independent P1 and P2 parameters, the patent allows P2 to be optimized for low on-resistance while P1 maintains breakdown voltage characteristics, eliminating the trade-off present in conventional designs.
Solution Approach 2:
The patent applies different pitch values to different spatial regions: larger P1 for column layer spacing (affecting breakdown voltage) and smaller P2 for body region spacing (affecting on-resistance). This local differentiation optimizes both characteristics simultaneously.
3Reliability
If the inter-column layer pitch is decreased to improve breakdown voltage, then the breakdown voltage increases, but the on-resistance increases
Solution Approach 1:
The independent pitch parameters P1 and P2 allow P1 to be optimized for breakdown voltage while P2 optimizes on-resistance, preventing the coupled deterioration seen in conventional designs.
Solution Approach 2:
The patent changes the conventional parameter relationship by introducing P2 as an independent variable with P2<P1, enabling simultaneous optimization of breakdown voltage (through P1) and on-resistance (through P2).
4Reliability
If the pitch parameters are independently optimized for best electrical characteristics, then the device performance improves, but the manufacturing complexity increases
Solution Approach 1:
While segmenting pitch control into P1 and P2 increases design complexity, the patent shows this can be implemented through standard multi-step photolithography processes, making the complexity manageable and worthwhile for the performance gains.
Data Source
AI summary
There is provided a semiconductor device including a semiconductor layer having a first conductivity type and including a first surface and a second surface on an opposite side of the first surface, a plurality of element structures formed in the first surface of the semiconductor layer at equal intervals in one direction, and a super junction structure formed in the semiconductor layer.