Super Junction MOSFET Gate Oxide Breakdown Prevention
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Solution Overview
Problem
In the reverse recovery process of super junction MOSFETs, the voltage generated in the p well regions below the gate pad electrode can lead to breakdown of the gate oxide film due to high resistance in the current path, causing short circuits and operational failures.
Innovation Solution
The semiconductor device features pn parallel columns with alternating conductivity type columns, wider second conductivity type well regions, and narrower second conductivity type channel regions, which reduce the voltage applied to the gate insulating film by lowering the current path resistance through the p well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the p well regions are made narrower to reduce device area, then the area occupied by p well regions is reduced, but the resistance of the current path through p well regions increases, leading to higher voltage applied to the gate oxide film and potential breakdown
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the p well structure. Specifically, it forms a first p-type impurity region with a first concentration and a second p-type impurity region with a second concentration that is higher than the first. This local variation in impurity concentration allows the p well to maintain low resistance in critical areas while occupying reduced overall area, thereby preventing gate oxide film breakdown without increasing device footprint.
2Reliability
If the p well regions are made wider to reduce current path resistance, then the voltage applied to the gate oxide film is reduced, but the area occupied by p well regions increases
Solution Approach 1:
The patent applies parameter changes by varying the impurity concentration parameter within the p well regions. Instead of uniformly increasing the width of p well regions to reduce resistance, the invention changes the electrical parameter (impurity concentration) to achieve lower resistance. The second p-type impurity region has a higher concentration than the first, which reduces the resistance of the current path through the p well without requiring increased area, thus maintaining compact device dimensions while ensuring gate oxide film reliability.
3Reliability
If additional p-type impurity regions are added to reduce current path resistance, then the voltage applied to the gate oxide film is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent applies merging by combining multiple p-type impurity regions with different concentrations into a unified p well structure. The first p-type impurity region and the second p-type impurity region are integrated within the same p well formation process and spatial arrangement. This merging approach reduces device complexity compared to implementing separate structures, while still achieving the goal of reducing current path resistance and preventing gate oxide film breakdown through the coordinated action of multiple impurity regions with varying concentrations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents breakdown of the gate insulating film during reverse recovery, ensuring proper operation of the super junction MOSFET by reducing the voltage applied to the gate oxide film.
Implementation Method 1
pn parallel columns, wherein first conductivity type columns and second conductivity type columns are alternately disposed
Implementation Method 2
the voltage generated in the p well regions below the gate pad electrode can lead to breakdown of the gate oxide film due to high resistance in the current path
Data Source
Figure 1(a)~1(b)
Figure 2(a)~2(c)
Figure 3~4
AI summary
A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. AMOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode. Therefore, it is possible to prevent breakdown of a portion of a gate insulating film immediately below the center of the gate pad electrode, and thus prevent breakdown of a semiconductor device.