Super Junction MOSFET Soft Recovery via Local Carrier Lifetime Control
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Solution Overview
Problem
Super junction MOSFETs exhibit hard recovery waveforms during reverse recovery operations, leading to sharp current and voltage rises, which result in noise and increased reverse recovery loss, limiting high-speed switching capabilities.
Innovation Solution
A semiconductor device with a parallel pn layer structure, where the p-type partition regions are replaced with n-type regions of lower impurity concentration, and a dual buffer layer configuration is implemented, with a high-concentration second buffer layer and a low-concentration first buffer layer, along with carrier lifetime adjustments using heavy metals or charged particle irradiation to shorten the carrier lifetime of the parallel pn layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If super junction MOSFETs use conventional structures with constant carrier lifetime in the depth direction, then the device achieves high breakdown voltage and low on-resistance, but exhibits hard recovery waveforms with sharp current and voltage rises during reverse recovery operations
Solution Approach 1:
The patent applies local quality by creating a non-uniform carrier lifetime distribution through selective heavy metal addition or charged particle irradiation in specific depth regions of the drift layer. This allows different portions of the device to have different carrier lifetime characteristics, with the irradiated region exhibiting shorter lifetime to suppress hard recovery waveform while maintaining overall high breakdown voltage and low on-resistance properties.
Solution Approach 2:
The patent changes the carrier lifetime parameter from constant to variable by introducing heavy metals (gold, platinum, copper, silver) or applying charged particle irradiation (protons, alpha particles, heavy ions). This parameter modification transforms the recovery waveform from hard to soft, reducing noise and reverse recovery loss while preserving the electrical characteristics.
2Speed
If the carrier lifetime is shortened to reduce reverse recovery time and achieve high-speed switching, then switching speed improves, but reverse recovery loss increases due to sharp current rises
Solution Approach 1:
The patent applies local quality by creating a non-uniform carrier lifetime distribution through selective heavy metal addition or charged particle irradiation in specific depth regions of the drift layer. This allows different portions of the device to have different carrier lifetime characteristics, with the irradiated region exhibiting shorter lifetime to suppress hard recovery waveform while maintaining overall high breakdown voltage and low on-resistance properties.
Solution Approach 2:
The patent changes the carrier lifetime parameter from constant to variable by introducing heavy metals (gold, platinum, copper, silver) or applying charged particle irradiation (protons, alpha particles, heavy ions). This parameter modification transforms the recovery waveform from hard to soft, reducing noise and reverse recovery loss while preserving the electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents sharp rises in reverse recovery current and time, enabling high-speed switching with reduced loss by achieving a soft recovery waveform and extending reverse recovery time, thus improving switching speed and reducing power losses.
Implementation Method 1
carrier lifetime adjustments using heavy metals or charged particle irradiation to shorten the carrier lifetime of the parallel pn layer
Data Source
AI summary
A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region.