Super Junction MOSFET P-Column Depth Variation for Avalanche Resistance
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Solution Overview
Problem
In the development of vertical-type power MOSFETs with a super junction structure, there is a trade-off between reducing on-resistance and maintaining high breakdown voltage, with existing methods either increasing on-resistance or compromising breakdown voltage.
Innovation Solution
The semiconductor device employs a super junction structure with p-type and n-type column regions alternately arranged, where the depth of the p-type column region in the cell region is made shallower than in the intermediate and peripheral regions, and a counter-doped region is used to reduce the effective p-type impurity concentration, allowing for improved avalanche resistance and reduced on-resistance while maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the super junction structure is adopted with uniform p-type column depth across all regions, then the breakdown voltage is maintained, but the on-resistance increases and avalanche resistance deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the depth of p-type column regions across different device regions. Specifically, the cell region has a first depth while the intermediate and peripheral regions have a second depth that is greater than the first depth. This localized structural variation allows each region to be optimized for its specific function: the cell region for low on-resistance and the intermediate/peripheral regions for high breakdown voltage and avalanche resistance.
2Reliability
If the p-type column region depth is increased to improve breakdown voltage, then the breakdown voltage is enhanced, but the on-resistance increases
Solution Approach 1:
The patent resolves this contradiction by implementing different p-type column depths in different regions. The cell region maintains a shallower first depth to minimize on-resistance for current conduction, while the intermediate and peripheral regions have a deeper second depth to enhance breakdown voltage and avalanche resistance. This spatial differentiation of structural parameters allows simultaneous optimization of both conflicting performance metrics.
3Reliability
If the super junction structure is adopted with deep p-type columns, then the breakdown voltage is maintained, but local current concentration occurs in intermediate and peripheral regions
Solution Approach 1:
The patent addresses local current concentration by making the p-type column regions in intermediate and peripheral regions deeper than those in the cell region. This deeper structure in the intermediate and peripheral regions redistributes the electric field and current density, preventing localized current concentration and improving avalanche resistance while maintaining the necessary breakdown voltage.
Data Source
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AI summary
In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).