Super Junction MOSFET Trap Level Depth Optimization
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Solution Overview
Problem
MOSFETs with super junction structures face challenges in shortening reverse recovery time while maintaining voltage withstand capability, as existing methods do not effectively manage carrier recombination and electric field distribution.
Innovation Solution
The semiconductor device incorporates a trap level region and an electric field concentration portion at different depth positions within the first pillar layer, along with a second pillar layer for charge balance, to facilitate fast carrier recombination and improved voltage withstand by optimizing the position and concentration of impurity regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a trap level is formed by irradiating a substrate with charging particles to shorten reverse recovery time, then reverse recovery time is reduced, but voltage withstand capability deteriorates due to crystal defects
Solution Approach 1:
The invention divides the semiconductor layer into multiple regions with different impurity concentrations and conductivity types, creating alternating columnar regions (first and second columnar regions) with different properties. This segmentation allows the trap level to be formed in specific regions without compromising the overall voltage withstand capability of the device.
Solution Approach 2:
The invention applies local quality by creating regions with different impurity concentrations and conductivity types in specific locations. The trap level is formed by irradiating specific regions with charging particles, while other regions maintain their original properties to ensure voltage withstand capability. This localized approach allows simultaneous optimization of reverse recovery time and voltage withstand capability.
2Reliability
If columnar regions are disposed alternately to create super junction structure, then voltage withstand capability is improved, but reverse recovery time increases due to carrier storage
Solution Approach 1:
The invention creates local quality differences by forming trap levels in specific columnar regions through selective irradiation with charging particles. This allows certain regions to facilitate fast carrier recombination while other regions maintain their voltage withstand function, resolving the contradiction between reverse recovery time and voltage withstand capability.
Solution Approach 2:
The invention changes the physical and chemical parameters of specific regions by irradiating them with charging particles to create trap levels. This modifies the carrier recombination characteristics in those regions without altering the overall super junction structure, enabling fast reverse recovery while maintaining voltage withstand capability.
3Reliability
If impurity concentration is increased to improve voltage withstand capability, then voltage withstand capability is enhanced, but reverse recovery time increases due to increased carrier storage
Solution Approach 1:
The invention applies local quality by creating regions with different impurity concentrations and conductivity types. High impurity concentration regions provide voltage withstand capability, while regions with trap levels formed by charging particle irradiation facilitate fast carrier recombination, achieving both goals simultaneously.
Solution Approach 2:
The invention segments the semiconductor layer into multiple columnar regions with different properties. This segmentation allows different regions to perform different functions: some regions maintain high voltage withstand capability through appropriate impurity concentrations, while other regions with trap levels enable fast reverse recovery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively shortens the reverse recovery time and enhances voltage withstand capability by ensuring charge balance and controlled electric field distribution, achieving improved reverse recovery characteristics.
Implementation Method 1
a trap level region, disposed inside the semiconductor layer and containing charged particles that form a trap level
Data Source
AI summary
A semiconductor device includes a semiconductor layer, having a drain region, a body region, and a source region, a gate electrode, facing the body region via a gate insulating film, a first pillar layer disposed inside the semiconductor layer so as to be continuous to the body region, and a trap level region, disposed inside the semiconductor layer and containing charged particles that form a trap level, and an electric field concentration portion, where an electric field concentrates in an off state in which a channel is not formed in the body region, and the trap level region are disposed at mutually different depth positions in a depth direction of the first pillar layer.