Super Junction MOSFET Trap Level Engineering

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Solution Overview

Problem

Super junction MOSFETs face increased reverse recovery time due to increased pn junction area, leading to longer turn-off switching times, while methods to shorten this time, such as heavy metal diffusion and electron irradiation, result in increased leakage current between the drain and source.

Innovation Solution

A semiconductor device with a super junction MOS structure where heavy particle irradiation is used to form a trap level locally in the column layer, reducing reverse recovery time without increasing leakage current, involving a high resistivity first base layer, drain, source, and gate insulating film, with a column layer opposing the drain, and source electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If heavy metal diffusion or electron irradiation is used to shorten reverse recovery time, then turn-off switching time is reduced, but leakage current between drain and source increases

Engineering Contradiction:
Improvereverse recovery timeVSAvoidleakage current
Core Design Contradiction:
Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The patent changes the physical state and properties of the columnar region by introducing trap levels through heavy particle irradiation. This modifies the electrical characteristics (carrier lifetime, conductivity) without adding metallic impurities, thereby reducing reverse recovery time while avoiding increased leakage current that would result from conventional heavy metal diffusion methods

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent substitutes heavy particle irradiation (creating intrinsic trap levels) for heavy metal diffusion methods. This replacement eliminates the harmful side effect of increased leakage current while achieving the desired reduction in reverse recovery time, as the trap levels are created through radiation damage rather than metallic contamination

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Power

If column layer is added to reduce on resistance and increase gate sensitivity, then turn-on switching performance improves, but pn junction area increases causing longer reverse recovery time

Engineering Contradiction:
Improvegate sensitivityVSAvoidreverse recovery time
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent applies local quality modification by introducing trap levels specifically in the columnar region through heavy particle irradiation. This localized treatment creates non-uniform electrical properties where the irradiated columnar regions have reduced carrier lifetime and improved reverse recovery characteristics, while maintaining the overall superjunction structure's low on-resistance and high gate sensitivity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the carrier lifetime parameter locally in the columnar region by creating trap levels through heavy particle irradiation. This parameter modification reduces the reverse recovery time without affecting the electrical characteristics (on-resistance, gate sensitivity) that depend on the overall superjunction structure

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively shortens reverse recovery time in super junction MOSFETs without increasing leakage current between the drain and source, improving switching performance by controlling trap levels and saturation current.

Implementation Method 1

heavy particle irradiation is performed to the column layer to form a trap level locally

Methodology Applied
Scientific EffectHeavy particle irradiation: Ion Beam

Data Source

PatentUS10672900B2Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same
Publication Date: 2020.06.02 ROHM CO LTD
  • US10672900B2 patent drawing
  • US10672900B2 patent drawing
  • US10672900B2 patent drawing

AI summary

A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.