Super Junction Semiconductor Device High Aspect Ratio P-Type Regions
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Solution Overview
Problem
Conventional methods for manufacturing super junction semiconductor devices face challenges in achieving a tradeoff between breakdown voltage and ON resistance, particularly in forming p-type regions with high aspect ratios, which leads to increased manufacturing costs and poor yield due to the need for expensive equipment and complex trench formation processes.
Innovation Solution
A method involving the formation of impurity diffusion trenches with a tapered cross-sectional shape, where p-type impurity regions are formed along the inner walls of these trenches through ion implantation, allowing for deeper diffusion and improved aspect ratio of p-type regions, thereby enhancing the tradeoff between breakdown voltage and ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multistage epitaxial method or trench filling epitaxial method is used to form p-type regions with high aspect ratio, then breakdown voltage and ON resistance tradeoff is improved, but manufacturing cost increases and yield decreases due to complex processes and expensive equipment
Solution Approach 1:
The patent divides the formation process into distinct stages: first forming trenches to a predetermined depth, then performing ion implantation to create p-type impurity regions along the trench walls, and finally performing heat treatment to diffuse the impurities. This segmentation allows each process to be optimized independently, achieving high aspect ratio p-type regions without requiring complex trench filling epitaxial equipment
Solution Approach 2:
The patent performs preliminary trench formation to a predetermined depth before ion implantation. This preliminary action creates a structured pathway that guides the subsequent ion implantation and diffusion processes, enabling precise control over p-type region formation and aspect ratio without requiring complex real-time process control equipment
2Length of stationary object
If p-type regions with high aspect ratio are formed using conventional methods, then vertical extension is achieved, but process complexity increases due to multiple ion implantation steps and thick resist masks
Solution Approach 1:
The patent performs ion implantation to a depth that extends beyond the trench depth, creating p-type impurity regions that originate from the trench walls and extend into the surrounding material. This partial excessive action ensures complete vertical coverage and facilitates the formation of high aspect ratio regions with a single implantation step rather than multiple staged implants
Solution Approach 2:
The patent utilizes heat treatment to change the physical state and distribution of the implanted p-type impurities. By controlling the temperature and duration of the heat treatment process, the impurities diffuse from the trench walls to form continuous vertical p-type regions, achieving the desired vertical extension without requiring multiple ion implantation steps or thick resist masks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of p-type regions with high aspect ratios that extend vertically, improving the tradeoff between breakdown voltage and ON resistance while reducing manufacturing costs and simplifying the process, leading to improved semiconductor device performance.
Implementation Method 1
forming a plurality of first-conductivity-type epitaxial layers (1-3) by epitaxial growth and stacking the plurality of first-conductivity-type epitaxial layers (1-3) on the n+-type starting substrate (110)
Implementation Method 2
forming a second-conductivity-type impurity region (51-53) in each of the plurality of first-conductivity-type epitaxial layers (1-3) by ion implanting a second-conductivity-type impurity in the each of the plurality of first-conductivity-type epitaxial layers (1-3)
Implementation Method 3
diffusing the second-conductivity-type impurity region (51-53) formed in the each of the plurality of first-conductivity-type epitaxial layers (1-3) by performing heat treatment
Implementation Method 4
connecting to each other in a depth direction (z), the second-conductivity-type impurity region (51-53) formed in the each of the plurality of first-conductivity-type epitaxial layers (1-3), and forming the second-conductivity-type region (62)
Data Source
AI summary
In each n-type epitaxial layer, p-type impurity regions are respectively formed by performing for each stacking of an n-type epitaxial layer, ion implantation using a resist mask. In a first n-type epitaxial layer, a p-type impurity region is formed at an inner wall of an impurity diffusion trench formed by dry etching. In a second and third n-type epitaxial layer, p-type impurity regions are formed respectively at an inner wall of impurity diffusion trenches that are recesses respectively corresponding to the impurity diffusion trenches of the first and the second n-type epitaxial layers respectively therebelow. The resist mask has an opening width that is wider than widths of open ends of the impurity diffusion trenches. The p-type impurity regions are connected by thermal diffusion processing, thereby forming a parallel pn layer constituted by p-type regions having a high aspect ratio and n-type regions respectively between the p-type regions.