Super Junction Column Implantation With Pattern-Deviation Feedback
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Solution Overview
Problem
Existing semiconductor devices with a super junction structure face challenges in achieving both low on-resistance and high breakdown voltage due to difficulties in forming n-type and p-type columns with high impurity concentrations, which can cause disruption of charge balance and defects during ion implantation.
Innovation Solution
A method is employed to form a super junction structure in a semiconductor device by using a shielding layer with pattern deviations to control the impurity concentration and position of n-type and p-type columns through feedback control, adjusting the implantation dose based on measured pattern deviations or misalignments to maintain charge balance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is performed to form n-type and p-type columns with high impurity concentrations, then low on-resistance is achieved, but charge balance is disrupted and defects occur
Solution Approach 1:
The patent employs feedback control by measuring the actual pattern of the shielding layer (which may have deviations from the design pattern) and using this measured information to adjust the ion implantation process. Specifically, the implantation dose is modified based on the measured pattern deviations to compensate for variations and maintain charge balance between n-type and p-type columns, thereby resolving the contradiction between achieving high impurity concentration and maintaining manufacturing precision
Solution Approach 2:
The patent changes the implantation dose parameter based on the measured pattern deviations of the shielding layer. By dynamically adjusting this parameter according to actual measurements, the system can compensate for manufacturing variations and maintain the desired charge balance while still achieving the required impurity concentrations for low on-resistance and high breakdown voltage
2Manufacturing precision
If shielding layer pattern is formed with high precision, then column positions are accurate, but manufacturing complexity increases
Solution Approach 1:
Rather than requiring extremely high precision in the shielding layer formation process, the patent uses feedback control to measure the actual pattern deviations and compensate for them in subsequent steps. This approach trades off some initial precision requirements for a more robust overall process that can handle normal manufacturing variations
Solution Approach 2:
The system performs self-correction by measuring its own pattern deviations and using this information to adjust subsequent processing steps. This self-service approach allows the manufacturing process to compensate for its own variations without requiring external intervention or extremely tight process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of a semiconductor device with balanced impurity concentrations in n-type and p-type columns, ensuring proper depletion and thus achieving high breakdown voltage and low on-resistance characteristics.
Implementation Method 1
forming a super junction structure in a semiconductor layer based on a pattern deviation of a shielding layer formed on a surface of the semiconductor layer relative to a design pattern, the shielding layer having an opening corresponding to at least one of an n-type column formation range where the n-type column is to be formed or a p-type column formation range where the p-type column is to be formed
Data Source
AI summary
In a method for manufacturing a semiconductor device having a semiconductor layer formed with a super junction structure in which an n-type column and a p-type column are alternately and repeatedly arranged at least in one direction, the super junction structure is formed in the semiconductor layer based on a pattern deviation of a shielding layer formed on a surface of the semiconductor layer relative to a design pattern, the shielding layer having an opening corresponding to at least one of an n-type column formation range where the n-type column is to be formed or a p-type column formation range where the p-type column is to be formed.