Super Junction Pillar Profile for Low-Oscillation Switching
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Solution Overview
Problem
Semiconductor devices with super junction structures experience oscillations during power element switching, leading to switching malfunctions and potential element destruction. Existing solutions that increase gate resistance and capacitance to reduce oscillations compromise switching efficiency.
Innovation Solution
A semiconductor device design featuring a substrate with an epitaxial layer, first and second gate electrodes, a first type body region, and a pillar region with specific width and thickness variations along the substrate's surface. This design reduces oscillations while maintaining low capacitance, particularly in low operating voltage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate resistance and capacitance are increased to reduce oscillations, then oscillation reduction is achieved, but switching efficiency deteriorates
Solution Approach 1:
The pillar region is designed with non-uniform width along the depth direction, creating different local capacitance characteristics at different depths. The upper portion has a larger width to reduce capacitance for high-voltage operation, while the lower portion has a smaller width to control oscillations, achieving localized optimization of electrical properties without uniformly increasing overall capacitance.
Solution Approach 2:
The patent changes the geometric parameters of the pillar region by varying its width along the depth direction. This parameter variation creates a capacitance profile that differs from conventional uniform structures, enabling oscillation suppression through specific capacitance characteristics while avoiding the need to uniformly increase gate capacitance and resistance, thereby preserving switching efficiency.
2Reliability
If switching speed is reduced to minimize oscillations, then oscillation reduction is achieved, but switching performance deteriorates
Solution Approach 1:
The non-uniform pillar width creates different electrical characteristics at different depths, allowing the structure to provide oscillation damping where needed while maintaining low overall capacitance for fast switching. The upper wider portion reduces capacitance for speed, while the lower narrower portion provides oscillation control.
Solution Approach 2:
The varying width profile of the pillar region creates a dynamic capacitance distribution that adapts to different operating conditions. The structure inherently provides different electrical characteristics during different phases of switching operation, enabling oscillation suppression without requiring uniform slowing of the switching process.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises: a substrate comprising an epitaxial layer; a first gate electrode and a second gate electrode disposed on the substrate; a first type body region disposed within the substrate between the first gate electrode and the second gate electrode, a pillar region extending from the first type body region toward a lower surface of the substrate and disposed within the epitaxial layer; and a first region and a second region of the pillar region, each comprising a portion whose width decreases and then increases along a first direction from an upper surface of the substrate toward the lower surface, wherein the first region is disposed between the first type body region and the second region, the first region comprises a first width that is a minimum width of widths of the pillar region and a second width that is greater than the first width, the second region comprises a third width that is greater than the first width and less than the second width, and the first region and the second region are divided with the second width as a boundary.