Super-junction Power Device Asymmetric Body Regions
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Solution Overview
Problem
Existing super-junction power devices experience significant oscillation in gate voltage due to sudden changes in gate-drain capacitance (Cgd) during turn-on and turn-off processes, leading to increased switching loss and reduced power conversion efficiency.
Innovation Solution
The semiconductor super-junction power device incorporates body regions with varying widths and unequal intervals between pillar epitaxial doped regions, along with a gate resistor and field oxide layer, to smooth the sudden change in Cgd, thereby reducing oscillation and improving switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If body regions with uniform width are used, then manufacturing process is simple, but gate-drain capacitance changes suddenly causing severe gate voltage oscillation
Solution Approach 1:
The patent applies asymmetry by designing body regions with different widths (first body region width different from second body region width) instead of uniform widths. This asymmetric structure causes the gate-drain capacitance to change gradually during switching transitions, reducing the sudden capacitance changes that cause gate voltage oscillation, while maintaining a manufacturable process.
Solution Approach 2:
The patent applies local quality by creating different body region widths at different locations (first body region vs second body region). The first body region has a different width than the second body region, allowing localized optimization of capacitance characteristics in different areas of the device to suppress oscillation while maintaining overall device functionality.
2Ease of manufacture
If pillar epitaxial doped regions with equal intervals are used, then device structure is regular and easy to manufacture, but switching speed is limited due to high miller capacitance
Solution Approach 1:
The patent applies asymmetry by setting different intervals between pillar epitaxial doped regions (first interval different from second interval) instead of using equal intervals throughout. This asymmetric spacing optimizes the electric field distribution and reduces miller capacitance effects, enabling faster switching speeds while maintaining a regular enough structure for manufacturing.
Solution Approach 2:
The patent applies parameter changes by varying the interval parameters between pillar epitaxial doped regions. The first interval and second interval are set to different values, changing the spatial parameters of the device structure to optimize capacitance characteristics and improve switching speed performance.
3Speed
If gate-drain capacitance changes rapidly during switching, then device responds quickly, but severe oscillation occurs in gate voltage
Solution Approach 1:
The patent applies asymmetry through different body region widths and different pillar intervals, which creates a more gradual capacitance transition during switching. This asymmetric structure prevents the sudden capacitance changes that generate severe oscillation, while still maintaining fast switching response through optimized charge balance in the super-junction structure.
Solution Approach 2:
The patent applies beforehand cushioning by designing the asymmetric body region structure in advance to prevent severe oscillation. The different body region widths and pillar intervals are configured beforehand to cushion the impact of capacitance changes during switching, reducing gate voltage oscillation before it can severely affect device performance.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductor power devices, and in particular relates to a semiconductor super-junction power device and a manufacturing method therefor. The super-junction power device of the present disclosure includes a termination region and a cell region; the cell region includes a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer, the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of JFET regions, a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions; the body regions have at least two unequal widths; two source regions are arranged in each of the body regions; a gate oxide layer is arranged on the body regions and the JFET regions; and a gate is arranged on the gate oxide layer.