Self-Aligned Gate Formation in Semiconductor Super-Junction Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and risk associated with the photoetching process in manufacturing semiconductor super-junction devices due to its high cost and alignment deviation issues.
Innovation Solution
A method that involves forming a hard mask layer on an n-type epitaxial layer, defining the position of a p-type column through photoetching, etching the hard mask layer to create a first trench with a wider opening, forming a sacrificial dielectric layer, and then etching to create a second trench, allowing for self-alignment of the gate formation, thus reducing the need for multiple photoetching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photoetching processes are performed to form the gate and p-type column separately, then the manufacturing precision and alignment accuracy are improved, but the manufacturing cost and manufacturing risk increase
Solution Approach 1:
The patent applies preliminary action by forming the gate structure first using photoetching, then using this pre-formed gate structure as a mask for subsequent etching to form the p-type column. This preliminary formation of the gate structure enables self-alignment without requiring additional photoetching steps, thereby reducing manufacturing cost while maintaining alignment accuracy.
Solution Approach 2:
The patent implements self-service by designing the process so that the gate structure itself serves as the mask for forming the p-type column. The gate structure automatically defines the alignment position of the p-type column through its physical presence as a mask layer, eliminating the need for separate photoetching alignment steps and reducing both cost and complexity.
2Manufacturing precision
If multiple photoetching processes are performed to form the gate and p-type column separately, then the manufacturing precision and alignment accuracy are improved, but the manufacturing complexity and manufacturing risk increase
Solution Approach 1:
The patent merges the gate formation process and the p-type column formation process into a single integrated sequence. The gate is formed first, then the same gate structure is used as a mask for forming the p-type column, combining what would traditionally be two separate photoetching processes into one continuous flow, thereby reducing manufacturing complexity while maintaining precision.
Solution Approach 2:
The gate structure serves multiple functions: it is both the final gate electrode and the mask for forming the p-type column. This multi-functionality eliminates the need for a separate dedicated mask layer and reduces the number of photoetching steps, simplifying the overall manufacturing process while ensuring precise alignment.
3Ease of manufacture
If a single photoetching process is used for both gate and p-type column formation, then the manufacturing cost and process complexity are reduced, but the alignment accuracy and manufacturing precision deteriorate
Solution Approach 1:
The gate structure serves itself as the alignment reference and mask for forming the p-type column. By using the gate's own physical structure as the mask, the process achieves automatic self-alignment without requiring separate photoetching steps, thereby maintaining high alignment accuracy while reducing manufacturing cost and complexity.
Solution Approach 2:
The gate structure is formed in advance as a preliminary step, and this pre-formed structure automatically defines the precise position for the p-type column. The preliminary gate formation creates the alignment reference that guides subsequent etching, ensuring high precision without additional photoetching alignment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces the manufacturing cost and risk of semiconductor super-junction devices by enabling gate formation in a self-alignment manner, requiring only a single photoetching process for both the gate and p-type column.
Implementation Method 1
the hard mask layer is etched, and at least one opening is formed in the hard mask layer
Implementation Method 2
The n-type epitaxial layer is etched with the hard mask layer as a mask, and a first trench is formed in the n-type epitaxial layer
Implementation Method 3
The n-type epitaxial layer is etched with the hard mask layer and the sacrificial dielectric layer as masks, and a second trench is formed in the n-type epitaxial layer
Implementation Method 4
a p-type column 13 is formed in the formed trench through an epitaxial process
Implementation Method 5
a pn junction structure is formed between the p-type column and the n-type epitaxial layer
Data Source
AI summary
Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.