Super Junction Semiconductor Device with Embedded P+ Region
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Solution Overview
Problem
Current semiconductor devices with super junction structures face limitations in enhancing avalanche resistance, particularly in planar type devices, where the avalanche resistance is not adequately improved compared to trench gate type devices.
Innovation Solution
The semiconductor device incorporates a super junction structure with a substrate having alternately arranged conductive type regions, a channel layer, and an embedded conductive type region with higher impurity concentration, which protrudes into the channel layer and contacts a contact conductive type region, facilitating easier electric field concentration and avalanche current flow, thereby improving avalanche resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar type super junction structure is used, then the device structure is simpler and manufacturing is easier, but the avalanche resistance is not adequately improved
Solution Approach 1:
The patent applies local quality by creating an embedded high impurity concentration region specifically at the corner of the P-type base region, rather than uniformly distributing impurities throughout the structure. This localized high impurity concentration area (with concentration higher than the surrounding P-type base region) provides enhanced avalanche resistance precisely where needed, while maintaining the overall simplicity of the planar structure and avoiding complex manufacturing processes throughout the entire device.
2Reliability
If the impurity concentration is increased in the P conductive type region, then the avalanche resistance is improved, but the device complexity increases
Solution Approach 1:
The patent implements local quality by concentrating the high impurity concentration region specifically at the corner of the P-type base region rather than increasing impurity concentration uniformly throughout the entire P-type region. This localized approach improves avalanche resistance at the critical breakdown point while avoiding the need to complexify the overall device structure or manufacturing processes across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively enhances avalanche resistance by concentrating the electric field around the embedded conductive type region, allowing for efficient avalanche current flow and reducing operation resistance, while maintaining a compact device design and simplified manufacturing process.
Implementation Method 1
concentrating the electric field around the embedded conductive type region, allowing for efficient avalanche current flow
Implementation Method 2
an avalanche current generated in the super junction structure is discharged to the contact P+ conductive type region via the P+ conductive type region. Specifically, when the break down occurs at the P conductive type region, the avalanche current is flown from the embedded P+ conductive type region to the contact P+ conductive type region
Data Source
AI summary
A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.