Super-Junction Semiconductor Fabrication via Ion Implantation
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Solution Overview
Problem
Conventional methods for fabricating semiconductor devices with super-junction structures, such as the multi-epi technology, are costly and time-consuming due to numerous fabrication steps, and they struggle to reduce the size of the semiconductor device while minimizing on-state resistance.
Innovation Solution
A semiconductor device with a super-junction structure is fabricated using a method that involves forming epitaxial layers, doping regions, and a gate dielectric layer without epitaxy-related steps, allowing for reduced fabrication time and costs, and enabling smaller device sizes by adjusting doping concentrations and energies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-epi technology is used to fabricate super-junction structure, then the withstand voltage capacity is improved, but the fabrication time and costs increase due to many repeating processing steps
Solution Approach 1:
The patent extracts and eliminates the epitaxial growth steps from the conventional multi-epi process. Instead of forming multiple epitaxial layers with alternating doping types through repeated epitaxial growth, the invention uses a single epitaxial layer and forms the super-junction structure through ion implantation and thermal diffusion processes alone, thereby reducing fabrication time while maintaining the charge balance and withstand voltage capacity
Solution Approach 2:
The patent changes the process parameters from epitaxial growth conditions to ion implantation and thermal diffusion conditions. By controlling implantation doses, energies, and thermal diffusion parameters, the invention achieves the same super-junction structure formation without the time-consuming epitaxial growth steps, resolving the contradiction between reliability improvement and fabrication time loss
2Reliability
If conventional multi-epi technology is used to fabricate super-junction structure, then the charge balance is achieved, but the device size cannot be reduced easily due to high fabrication costs and complexity
Solution Approach 1:
The patent removes the complex repeating epitaxial growth steps from the fabrication process. The super-junction structure is formed using simpler ion implantation and thermal diffusion processes on a single epitaxial layer, reducing fabrication process complexity while maintaining charge balance through controlled dopant diffusion
Solution Approach 2:
The invention changes from controlling epitaxial growth parameters to controlling ion implantation and thermal diffusion parameters. This parameter transformation simplifies the fabrication process while enabling precise control over dopant distribution and charge balance, thereby reducing device complexity
3Reliability
If doping concentration of N-type epitaxial drift region is reduced and thickness is increased to improve withstand voltage capacity, then the withstand voltage capacity is improved, but the on-state resistance increases
Solution Approach 1:
The patent applies local quality by creating alternating doped and undoped regions within the drift region through the super-junction structure. The doped columns provide localized charge balance and electric field modulation, allowing the overall drift region to maintain higher doping concentration and thinner thickness while still achieving high withstand voltage capacity. This local structuring reduces on-state resistance compared to uniformly doped structures
Solution Approach 2:
The invention creates a composite structure within the drift region by combining doped and undoped semiconductor regions in an alternating pattern. This composite super-junction structure enables simultaneous achievement of high breakdown voltage and low on-state resistance by leveraging the electric field distribution characteristics of the composite architecture, avoiding the trade-off present in uniformly doped structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces fabrication time and costs, achieves charge balance, and allows for smaller device sizes while minimizing on-state resistance, improving the overall efficiency and performance of the semiconductor device.
Implementation Method 1
performing an implanting process, implanting dopants of a second conductivity type in the undoped polysilicon layer, thereby forming a doped polysilicon layer having the second conductivity type in the opening
Implementation Method 2
performing a thermal process to diffuse the dopants in the doped polysilicon layer into the epitaxial layer adjacent thereto, thereby forming a third doping region having the second conductivity type in the epitaxial layer
Data Source
AI summary
A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.