Super-junction Semiconductor Manufacturing via Ion Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for manufacturing super-junction semiconductor devices, such as the multi-stage epitaxial growth method and trench embedding method, are costly and difficult to control in terms of impurity concentration and thickness, and they fail to effectively improve the trade-off relationship between Eoff (turning OFF loss) and dV/dt (voltage change over time) in the OFF state, especially with variable gate resistance.
Innovation Solution
A method involving trench embedding to form high concentration layers with high accuracy, using epitaxial growth to create a parallel pn layer, followed by heavy particle irradiation to form a donor layer that enhances impurity concentration and thickness control, thereby improving the trade-off relationship between Eoff and dV/dt without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-stage epitaxial growth method is used to manufacture super-junction semiconductor device, then parallel pn layer can be formed, but impurity concentration and thickness are difficult to control with high precision
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the substrate and the parallel pn layer. This buffer layer serves as a foundation that enables precise control of the subsequent parallel pn layer's impurity concentration and thickness, while simplifying the overall manufacturing process by providing a stable starting point for epitaxial growth.
Solution Approach 2:
The patent employs ion implantation to precisely control the impurity concentration in the parallel pn layer. By adjusting ion implantation parameters (dose, energy, distribution), the method achieves high-precision control of impurity concentration and thickness without increasing manufacturing complexity, directly resolving the technical contradiction.
2Productivity
If conventional methods are used to manufacture super-junction semiconductor device, then production cost is high, but manufacturing efficiency is low
Solution Approach 1:
The patent extracts and eliminates unnecessary manufacturing steps from conventional methods. By using a simplified buffer layer approach combined with ion implantation, the method removes redundant epitaxial growth stages, thereby improving manufacturing efficiency while reducing production costs.
Solution Approach 2:
The patent employs a cost-effective ion implantation process that uses consumable ion sources to precisely dope the parallel pn layer. This approach replaces expensive and time-consuming multi-stage epitaxial growth with a more efficient, lower-cost ion implantation method, improving productivity while reducing manufacturing costs.
3Object-affected harmful factors
If gate resistance is increased to reduce dV/dt, then Eoff increases due to longer charge discharge time
Solution Approach 1:
The patent introduces a high concentration layer locally within the parallel pn layer structure. This localized high concentration region modifies the electric field distribution and charge carrier behavior specifically in the critical region, enabling reduced dV/dt without requiring increased gate resistance, thus avoiding the penalty of increased Eoff.
Solution Approach 2:
The patent changes the physical and electrical parameters of the parallel pn layer by introducing a high concentration layer with different impurity concentration. This parameter change alters the charge discharge characteristics, enabling faster dV/dt control without increasing gate resistance, thereby reducing Eoff while maintaining proper dV/dt control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing costs and improves the trade-off relationship between Eoff and dV/dt by forming high concentration regions with precise impurity concentration and thickness, leading to increased production efficiency and reduced defective products.
Implementation Method 1
the high resistivity n− drift layer is depleted in the OFF state to enhance the withstand voltage. Consequently, a thin n− drift layer narrows the width of the depletion layer starting from the pn junction
Implementation Method 2
forming a first semiconductor layer of a first conductivity type with a lower concentration than a high concentration semiconductor substrate on the semiconductor substrate by means of an epitaxial growth process
Implementation Method 3
forming a heavy particle irradiation layer by irradiating heavy particles from the back side of the semiconductor substrate into a portion of the parallel pn layer beneath the device surface structure
Implementation Method 4
forming a third semiconductor layer of the first conductivity type with an impurity concentration lower than that of the second semiconductor layer and higher than that of the first semiconductor layer by transforming the heavy particles in the heavy particle irradiation layer formed by the heavy particle irradiation into donors through a heat treatment process
Data Source
AI summary
A method of manufacturing a super-junction semiconductor device is disclosed that allows forming a high concentration layer with high precision and improves the trade-off relationship between the Eoff and the dV/dt. The method comprises a step of forming a parallel pn layer and a step of forming a proton irradiated layer in the upper region of the pn layer. Then, heat treatment is conducted on the proton irradiated layer for transforming the protons into donors to form a high concentration n type semiconductor layer.