Super Junction Semiconductor Device with Stepped Corner Regions
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Solution Overview
Problem
Heretofore known super junction semiconductor devices face issues with local electric field concentration and breakdown voltage drop due to charge imbalance and impurity concentration differences between the element active and breakdown voltage structure portions, particularly in corner regions where the pitch of n-type and p-type regions differs.
Innovation Solution
A semiconductor device with a first parallel pn layer in the element active portion and a second parallel pn layer in the breakdown voltage structure portion, where the second layer has a narrower pitch and lower average impurity concentration, and an intermediate region with further reduced impurity concentrations, is designed to maintain charge balance and prevent breakdown voltage drops by diffusing impurity implantation regions and forming stepped regions in the corner portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the pitch of n-type and p-type regions is narrowed in the breakdown voltage structure portion to increase breakdown voltage, then the breakdown voltage is improved, but the on-resistance increases
Solution Approach 1:
The patent applies different pitch values for different regions: a first pitch in the element active portion and a second (narrower) pitch in the breakdown voltage structure portion. This local differentiation allows the breakdown voltage structure to have higher breakdown voltage while the element active portion maintains lower on-resistance through its wider pitch configuration.
2Reliability
If the impurity concentration of the parallel pn layer is increased to reduce on-resistance, then the on-resistance is reduced, but the breakdown voltage decreases
Solution Approach 1:
The patent sets different impurity concentrations for different regions: higher impurity concentration in the element active portion to reduce on-resistance, and lower impurity concentration in the breakdown voltage structure portion to maintain high breakdown voltage. This spatial differentiation resolves the contradiction between on-resistance and breakdown voltage.
3Ease of manufacture
If the pitch of n-type and p-type regions is made uniform across the chip, then the manufacturing process is simplified, but local electric field concentration occurs in corner regions causing breakdown voltage drop
Solution Approach 1:
The patent introduces different pitch values for different regions (first pitch for element active portion, second pitch for breakdown voltage structure portion) to prevent local electric field concentration in corner regions. This local differentiation maintains high breakdown voltage while the manufacturing process remains relatively simple through standardized implantation steps.
4Strength
If the repeated pitch of n-type and p-type regions is narrowed in the breakdown voltage structure portion, then the breakdown voltage is enhanced, but the charge balance between element active and breakdown voltage structure portions becomes imbalanced
Solution Approach 1:
The patent carefully designs the pitch differentiation to achieve both high breakdown voltage and charge balance. By setting appropriate pitch values for each region and controlling the extension of impurity implantation regions, the patent ensures that the depletion layers from both regions meet at the same depth, maintaining charge balance while achieving the desired breakdown voltage enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-resistance while maintaining a higher breakdown voltage difference between the element peripheral and active portions, suppressing partial breakdown voltage drops and enhancing the overall reliability and avalanche resistance.
Implementation Method 1
a heat treatment step is carried out. In the heat treatment step, the first first conductivity type impurity implantation regions and the first second conductivity type impurity implantation regions are diffused, thus forming a first parallel pn layer
Implementation Method 2
a heat treatment step is carried out. In the heat treatment step, the first first conductivity type impurity implantation regions and the first second conductivity type impurity implantation regions are diffused
Data Source
AI summary
A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn layer in a breakdown voltage structure portion. Corner portions of the first parallel pn layer has a plan view shape where stepped regions formed by shortening the length of the first n-type and p-type regions in steps are disposed in a stepwise arrangement. The stepped regions continue with a second parallel pn layer via an intermediate region lower in average impurity concentration than the first parallel pn layer.