Super Junction Semiconductor Device with Vertical Gate Structure
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Solution Overview
Problem
Conventional super junction semiconductor devices experience oscillation issues due to reduced mirror capacitance, which affects switching characteristics and noise during switching operations.
Innovation Solution
A super junction semiconductor device is designed with a blocking layer comprising first and second conductive type pillars that are stacked and overlapped in the vertical direction, along with a gate structure extending horizontally and electrically connected to these pillars, increasing the volume of the first conductivity type pillars to enhance mirror capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate structures are made small to decrease gate charges, then the device complexity is reduced, but the mirror capacitance decreases causing oscillation
Solution Approach 1:
The patent transitions from a two-dimensional planar gate structure to a three-dimensional structure by forming gate electrodes that extend vertically along the sidewalls of the pillars. This vertical extension increases the gate-drain overlap area and mirror capacitance without increasing the horizontal footprint, thus maintaining low device complexity while improving reliability.
Solution Approach 2:
The gate electrode is positioned within the trench structure formed between the pillars, nesting the gate structure within the existing pillar arrangement. This allows the gate to closely follow the pillar sidewalls, maximizing the overlap area for mirror capacitance while utilizing the existing spatial configuration efficiently.
2Area of stationary object
If the sidewall extends linearly in vertical direction, then the gate structure area is minimized, but oscillation occurs due to reduced mirror capacitance
Solution Approach 1:
Instead of extending the sidewall linearly in only the vertical direction, the patent introduces a horizontal component by forming the gate electrode to extend along the sidewall surface. This creates a three-dimensional gate structure that increases the overlap area with the drain region, thereby increasing mirror capacitance and suppressing oscillation while keeping the overall device footprint compact.
3Reliability
If the volume of first conductivity type pillars is increased to enhance mirror capacitance, then oscillation is suppressed, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the pillar structure into first conductivity type pillars and second conductivity type pillars arranged in an alternating pattern. This segmentation allows independent control and optimization of each pillar type's dimensions and doping characteristics, making it easier to achieve the desired mirror capacitance without excessively complex manufacturing requirements.
Solution Approach 2:
The patent applies different doping concentrations and pillar dimensions locally - the first conductivity type pillars have specific doping levels and sizes optimized for mirror capacitance, while the second conductivity type pillars have complementary properties. This local optimization allows achieving high reliability through enhanced mirror capacitance without requiring uniform high precision across the entire device structure.
Data Source
AI summary
A super junction semiconductor device includes a substrate having a first conductive type, a blocking layer positioned on the substrate, the blocking layer including first conductive type pillars and second conductive type pillars, each extending in a vertical direction and arranging alternatively in a horizontal direction, and a gate structure disposed on the blocking layer, the gate structure extending in the horizontal direction and being electrically connected to ones of the first and second conductive type pillars. Thus, oscillation phenomena may be suppressed.