Super Junction Semiconductor Structure for Fast Switching and Surge Current
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Solution Overview
Problem
Existing power control semiconductor devices face challenges in reducing on-resistance and improving switching speed and current withstand capabilities.
Innovation Solution
A semiconductor device with a super junction structure is designed, incorporating multiple semiconductor layers and a control electrode configuration that enhances hole rejection and reduces hole ejection resistance, thereby improving switching speed and current withstand capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but on-resistance cannot be reduced sufficiently
Solution Approach 1:
The semiconductor device is divided into multiple alternating layers of first conductive type (n-type) and second conductive type (p-type), creating a segmented super junction structure. This segmentation allows simultaneous achievement of low on-resistance and high breakdown voltage by distributing the electric field across multiple junctions, thereby improving switching speed without excessive complexity increase.
Solution Approach 2:
Different regions of the semiconductor device are assigned different conductive types and doping concentrations to optimize local properties. The alternating n-type and p-type layers create localized regions with specific electrical characteristics, enabling reduced on-resistance in certain areas while maintaining high breakdown voltage in others, thus improving switching speed.
2Reliability
If semiconductor layers are added to reduce on-resistance, then current withstand improves, but device complexity increases
Solution Approach 1:
The device uses segmented alternating layers of different conductive types to distribute current flow paths. This segmentation allows the device to handle higher currents by providing multiple parallel conduction paths while keeping each individual layer relatively simple, thus improving current withstand capacity without proportionally increasing overall device complexity.
Solution Approach 2:
The semiconductor device employs a composite structure combining multiple layers of different conductive types (n-type and p-type) with different doping concentrations. This composite approach enables the device to achieve superior current withstand capacity by leveraging the complementary properties of different material regions, rather than requiring a single complex material system.
3Speed
If switching speed is improved through structure optimization, then on-resistance decreases, but breakdown voltage may be compromised
Solution Approach 1:
The alternating n-type and p-type layers create multiple junctions that segment the electric field path. This segmentation allows the device to maintain high breakdown voltage by distributing the electric field stress across multiple interfaces, while simultaneously achieving low on-resistance through optimized carrier transport in each layer, thus improving switching speed without compromising breakdown voltage.
Solution Approach 2:
The invention optimizes parameters such as doping concentrations, layer thicknesses, and junction depths in the alternating conductive type layers. By carefully adjusting these parameters, the device achieves a balance between low on-resistance (for fast switching) and high breakdown voltage, allowing switching speed improvement without sacrificing voltage withstand capability.
Data Source
AI summary
A semiconductor device includes first, second and control electrodes, and a semiconductor part between the first and second electrode. The semiconductor part includes first and third layers of a first conductive type, and second, fourth and fifth layers of a second conductive type. The first layer extends between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is partially provided on the second layer between the second layer and the second electrode. A first fourth layer and a second fourth layer are provided in the first layer. The fifth layer is provided between the first layer and the second layer. The fifth layer is partially provided on the first layer between the first fourth layer and the second fourth layer. The control electrode is provided between the second electrode and each of the fourth layers.