Super Junction Semiconductor Termination Structure Design
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Solution Overview
Problem
Super junction semiconductor devices face challenges in achieving an optimal trade-off between on-state resistance and breakdown voltage due to limitations in setting precise lateral charge balance and reducing electric field strength outside the transistor cell area.
Innovation Solution
The semiconductor device incorporates a super junction structure with alternately arranged drift and compensation sub-regions of opposite conductivity types, along with a termination area that includes specific termination sub-regions to improve voltage absorption and reduce the size of the termination area, allowing for better utilization of semiconductor volume and enhanced voltage blocking capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional super junction structure is used with alternately arranged drift and compensation sub-regions, then the trade-off between on-state resistance and breakdown voltage is improved, but the lateral charge balance precision is insufficient and the electric field strength cannot be adequately reduced outside the transistor cell area
Solution Approach 1:
The termination area is segmented into multiple sub-regions: first termination sub-regions of the first conductivity type, second termination sub-regions of the second conductivity type, and third termination sub-regions of the first conductivity type. This segmentation allows independent optimization of charge distribution in different areas, enabling precise lateral charge balance compensation and effective electric field reduction at the device periphery.
Solution Approach 2:
Different termination sub-regions are assigned different conductivity types and doping characteristics tailored to their specific functional requirements. The first termination sub-regions provide voltage blocking, the second termination sub-regions provide charge compensation, and the third termination sub-regions provide additional voltage absorption. This local differentiation enables precise control of charge balance and electric field distribution.
2Reliability
If the termination area is enlarged to improve voltage absorption and electric field management, then the voltage blocking capability is enhanced, but the semiconductor volume utilization is reduced
Solution Approach 1:
The termination structure utilizes the vertical dimension by stacking multiple termination sub-regions with alternating conductivity types along the vertical direction. This three-dimensional arrangement provides enhanced voltage absorption and electric field management capabilities while maintaining a compact lateral footprint, thereby improving volume utilization efficiency.
Solution Approach 2:
The termination area employs a composite structure combining regions of first conductivity type and second conductivity type in an alternating pattern. This composite arrangement creates a multi-layered charge distribution that enhances voltage blocking capability through synergistic interaction between adjacent sub-regions of opposite polarity, achieving superior performance in a compact volume.
3Ease of manufacture
If the lateral charge balance is set with conventional methods, then the super junction structure can be formed, but the precision of charge balance setting is insufficient leading to suboptimal performance
Solution Approach 1:
The termination sub-regions are pre-configured with specific conductivity types and doping profiles before final device operation. The first termination sub-regions are prepared with the first conductivity type, interspersed with second termination sub-regions of the second conductivity type, creating a pre-established charge compensation network that automatically balances lateral charge distribution during device fabrication and operation.
Solution Approach 2:
The second termination sub-regions of the second conductivity type act as intermediary elements between the first termination sub-regions of the first conductivity type. These intermediary regions provide localized charge compensation and facilitate smooth charge transition, enabling precise lateral charge balance setting while maintaining ease of manufacturing through standard super junction fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of super junction semiconductor devices by improving voltage absorption and reducing the termination area size, leading to improved voltage blocking capabilities and a more efficient use of semiconductor volume.
Implementation Method 1
mutual space charge compensation of n- and p-doped regions in a semiconductor substrate or body allowing for an improved trade-off between area-specific on-state resistance Ron×A and breakdown voltage Vbr
Implementation Method 2
Performance of charge compensation of SJ semiconductor devices depends on precision when setting a lateral or horizontal charge balance by the n-doped and p-doped regions and when reducing an electric field strength in an area outside a transistor cell area
Data Source
AI summary
A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.


