Super-junction Semiconductor Device Transient On-Resistance Reduction
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Solution Overview
Problem
In super-junction semiconductor devices with parallel super-junction and MOS cell stripes, the p column over which no MOS cell stripe is arranged becomes electrically floating, leading to increased on-resistance during switching operations due to charge accumulation and depletion layer extension.
Innovation Solution
Conductive connections are established between the ends of p columns with and without MOS cell stripes to ensure shared potential, preventing floating potential and reducing transient on-resistance by allowing quick discharge of charges during switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width (Lg) is increased to adjust the gate-drain capacity Cgd to an appropriate value, then the switching characteristics improve, but the device complexity increases due to the need for precise positional alignment between p columns and MOS cell stripes
Solution Approach 1:
The invention divides the gate structure into multiple segments corresponding to different p column groups. By segmenting the gate electrode into distinct regions that can be independently positioned and sized, the patent enables flexible adjustment of gate width for different p columns, allowing optimization of gate-drain capacity without requiring precise alignment across the entire device structure.
Solution Approach 2:
The patent introduces an additional degree of freedom by allowing the gate electrode to extend beyond the immediate p column region in the lateral dimension. This dimensional extension enables the gate to overlap with multiple p columns simultaneously, providing another dimension for adjusting gate-drain capacity independent of the vertical alignment between p columns and MOS cell stripes.
2Manufacturing precision
If the p column is arranged to support MOS cell stripe positioning, then the manufacturing precision is improved, but the gate width (Lg) becomes intrinsically narrow limiting adjustable magnitude
Solution Approach 1:
The invention merges the gate electrode structure with the p column structure by allowing the gate to extend laterally beyond the immediate p column region. This merging enables the gate to simultaneously serve multiple functions: maintaining precise positioning relative to p columns while extending to provide adequate gate width for adjusting gate-drain capacity, thus combining positioning precision with sufficient dimensional size.
Solution Approach 2:
The patent creates a dynamic gate structure that can be selectively extended or positioned to overlap with different numbers of p columns. This dynamic configuration allows the gate width to be adjusted based on operational requirements while maintaining the underlying p column positioning structure, enabling flexible optimization of gate-drain capacity without being constrained by fixed geometric relationships.
Data Source
AI summary
Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.