Super Junction Trench MOSFET Layout for Resistance-Voltage Balance
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Solution Overview
Problem
Existing semiconductor devices with narrow mesa structures combined with super junction structures face deterioration in resistance-withstand voltage relationships due to imbalanced ratios between p-type and n-type pillar layers.
Innovation Solution
A semiconductor device design featuring a narrow mesa structure with electric field relieving layers and a super junction structure, where the first pillar layers are narrower than the electric field relieving layers, and the second pillar layers are wider than the mesa regions, optimizing the ratio and maintaining the resistance-withstand voltage relationship.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a narrow mesa structure is combined with a super junction structure, then channel resistance is reduced, but the resistance-withstand voltage relationship deteriorates due to imbalance in p-type and n-type pillar layers
Solution Approach 1:
The patent applies local quality by differentiating the width dimensions between first pillar layers and second pillar layers within the super junction structure. Specifically, the first pillar layers (p-type) are configured with a first width while the second pillar layers (n-type) have a second width that differs from the first, creating localized structural variations that optimize both channel resistance and withstand voltage characteristics in different regions of the device
Solution Approach 2:
The patent implements asymmetry by intentionally creating unequal width dimensions between the p-type and n-type pillar layers in the super junction structure. This asymmetric design breaks the conventional symmetric super junction configuration, allowing independent optimization of each pillar layer's dimensions to simultaneously achieve low channel resistance and high withstand voltage capability
2Reliability
If the width of the first pillar layer is reduced to match or be less than the electric field relieving layer, then the resistance-withstand voltage relationship is maintained, but the super junction structure becomes more complex
Solution Approach 1:
The patent applies parameter changes by systematically varying the width dimensions of different pillar layers and the electric field relieving layer. The first pillar layer width is specifically controlled to be equal to or less than the electric field relieving layer width, while the second pillar layer has a different width, creating a multi-parameter optimized structure that maintains reliability without excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized design maintains a favorable resistance-withstand voltage relationship by reducing channel resistance and improving current path efficiency, enhancing the overall performance of the semiconductor device.
Implementation Method 1
a p-type electric field relieving layer is provided on the bottom of the trench to allow a depletion layer to extend the bottom of the trench
Implementation Method 2
When a gate voltage is applied to a gate structure, an inversion layer (channel) is formed only on a surface portion of a semiconductor layer facing the gate structure
Implementation Method 3
The super junction structure is capable of holding a withstand voltage by a depletion layer extending between the p-type pillar layer and the n-type pillar layer
Data Source
AI summary
A semiconductor device includes a plurality of trenches penetrating through a source region and a base region, and a mesa region as a region between two of the plurality of trenches. A gate electrode that faces the base region with a gate insulating film interposed between the gate electrode and the base region is formed in each trench. An electric field relieving layer is provided immediately below each trench. A super junction structure in which a first pillar layer and a second pillar layer are alternately arranged is formed between the base region and the drift layer. A width of the first pillar layer is equal to or less than a width of the electric field relieving layer.