Super Junction VDMOS Gate Charge Reduction via Folded Polysilicon
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Solution Overview
Problem
Current VDMOS devices have high gate charge (Qg) leading to high Figure of Merit (FOM), resulting in significant power loss, especially in applications where switching loss is dominant, and existing methods to reduce Qg often increase the 'on' resistance (Rds(on)) or have minimal impact on gate to source charge (Qgs).
Innovation Solution
The design involves removing one of the two source contacts and significantly reducing the polysilicon gate length in a Super Junction VDMOS device, maintaining the other structures, which reduces Qg without increasing Rds(on), thereby improving the FOM. This configuration can be adapted to other vertical devices with symmetrical source contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate polysilicon length is reduced to decrease gate charge, then gate charge Qg decreases, but the on-resistance Rds(on) increases
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a 3D folded gate structure. The gate polysilicon is folded back underneath the source contact, creating vertical and horizontal components that increase the effective gate length without increasing the planar footprint. This dimensional transformation allows achieving low gate charge while maintaining low on-resistance by effectively increasing the gate control area.
Solution Approach 2:
The gate structure is folded back underneath the source contact, creating a nested configuration where the gate extends under the source region. This nesting allows the gate to overlap with both the drain and source regions, increasing the effective gate length and improving electrical field control without increasing the device's planar dimensions.
2Quantity of substance
If a split gate structure is used to reduce gate charge, then gate to drain charge Qgd decreases, but the impact on gate to source charge Qgs is minimal
Solution Approach 1:
The folded gate structure creates asymmetric overlap regions with the source and drain. By folding the gate underneath the source contact, the structure achieves significant gate-to-source overlap while maintaining controlled gate-to-drain overlap. This asymmetric configuration allows independent optimization of Qgs and Qgd, addressing both parameters effectively.
3Speed
If the gate length is significantly reduced, then switching performance improves, but the device complexity increases
Solution Approach 1:
The folded gate structure introduces dynamic spatial utilization where the gate polysilicon serves multiple spatial functions. The same gate material is positioned to simultaneously control both source and drain regions through its folded configuration, achieving enhanced switching performance without proportionally increasing manufacturing complexity.
Data Source
AI summary
A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.